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i965: Use 3D clears on gen6+ to avoid inter-ring synchronization.
author
Eric Anholt
<eric@anholt.net>
Thu, 19 May 2011 18:02:14 +0000
(11:02 -0700)
committer
Eric Anholt
<eric@anholt.net>
Mon, 25 Jul 2011 20:47:18 +0000
(13:47 -0700)
Improves firefox-talos-gfx around 5%.
src/mesa/drivers/dri/intel/intel_clear.c
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diff --git
a/src/mesa/drivers/dri/intel/intel_clear.c
b/src/mesa/drivers/dri/intel/intel_clear.c
index 81c062fba538dfc7aceaa18a0a8f56d7bb708494..76d33f9b37e2d4efda64ba6ee5dc57f787c6efb0 100644
(file)
--- a/
src/mesa/drivers/dri/intel/intel_clear.c
+++ b/
src/mesa/drivers/dri/intel/intel_clear.c
@@
-116,13
+116,13
@@
intelClear(struct gl_context *ctx, GLbitfield mask)
}
/* HW color buffers (front, back, aux, generic FBO, etc) */
- if (colorMask == ~0) {
+ if (
intel->gen < 6 &&
colorMask == ~0) {
/* clear all R,G,B,A */
blit_mask |= (mask & BUFFER_BITS_COLOR);
}
else {
/* glColorMask in effect */
- tri_mask |= (mask &
(BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_BACK_LEFT)
);
+ tri_mask |= (mask &
BUFFER_BITS_COLOR
);
}
/* Make sure we have up to date buffers before we start looking at