Optimize i?86-*-elfiamcu for iamcu by default

Default -mtune=/-march= to iamcu for i[34567]86-*-elfiamcu targets.

	* config.gcc (x86_archs): Add iamcu.
	(with_cpu): Default to iamcu for i[34567]86-*-elfiamcu.
	(with_arch): Likewise.
	* doc/invoke.texi: Add iamcu.

From-SVN: r225464

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 2b3af82be940dae3200681e629b3e4f1ca3b7326..f0405fe2bcd780402a38ab5e6a8f1ad656e30bc4 100644 (file)
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -585,7 +585,7 @@ tm_defines="$tm_defines LIBC_GLIBC=1 LIBC_UCLIBC=2 LIBC_BIONIC=3 LIBC_MUSL=4"
 x86_archs="athlon athlon-4 athlon-fx athlon-mp athlon-tbird \
 athlon-xp k6 k6-2 k6-3 geode c3 c3-2 winchip-c6 winchip2 i386 i486 \
 i586 i686 pentium pentium-m pentium-mmx pentium2 pentium3 pentium3m \
-pentium4 pentium4m pentiumpro prescott"
+pentium4 pentium4m pentiumpro prescott iamcu"
 
 # 64-bit x86 processors supported by --with-arch=.  Each processor
 # MUST be separated by exactly one space.
@@ -3278,6 +3278,9 @@ esac
 # This block sets nothing except for with_cpu.
 if test x$with_cpu = x ; then
   case ${target} in
+    i[34567]86-*-elfiamcu)
+      with_cpu=iamcu
+      ;;
     i[34567]86-*-*|x86_64-*-*)
       with_cpu=$cpu
       ;;
@@ -3370,6 +3373,9 @@ if test x$with_arch = x ; then
       # Default arch is set via TARGET_SUBTARGET32_ISA_DEFAULT
       # and TARGET_SUBTARGET64_ISA_DEFAULT in config/i386/darwin.h.
       ;;
+    i[34567]86-*-elfiamcu)
+      with_arch=iamcu
+      ;;
     i[34567]86-*-*)
       # --with-fpmath sets the default ISA to SSE2, which is the same
       # ISA supported by Pentium 4.

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 69ae0c35da5fe999dc2436d7855ff65e073b234e..b28e5d60f5c9180f53e7f10df76f7a3fc31964f4 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -22250,6 +22250,9 @@ Intel i486 CPU@.  (No scheduling is implemented for this chip.)
 @itemx pentium
 Intel Pentium CPU with no MMX support.
 
+@item iamcu
+Intel MCU, based on Intel Pentium CPU.
+
 @item pentium-mmx
 Intel Pentium MMX CPU, based on Pentium core with MMX instruction set support.