lm32: replace $clog2 with macro

Unfortunately, XST does not support $clog2 with the localparam keyword
(the parameter keyword works just fine). Define a macro which replaces the
call with a constant function.

This commit can be reverted if the bug in XST is fixed.

Signed-off-by: Michael Walle <michael@walle.cc>

diff --git a/verilog/lm32/lm32_config.v b/verilog/lm32/lm32_config.v
index bf49a6fc9d52c9eb8468f2bf6e04602ca4be7e02..3c2006f5a4a985d4d75f0f99b3f06cddb051fac4 100644 (file)
--- a/verilog/lm32/lm32_config.v
+++ b/verilog/lm32/lm32_config.v
@@ -36,4 +36,15 @@
 //`define CFG_EXTERNAL_BREAK_ENABLED
 //`define CFG_GDBSTUB_ENABLED
 
+function integer clog2;
+  input integer value;
+  begin
+    value = value - 1;
+    for (clog2 = 0; value > 0; clog2 = clog2 + 1)
+      value = value >> 1;
+  end
+endfunction
+
+`define CLOG2 clog2
+
 `endif

diff --git a/verilog/lm32/lm32_dcache.v b/verilog/lm32/lm32_dcache.v
index 7b3799e33c7bf692a80f405501dbf5bf211346a2..fd507803236af427da5f56a4fb9896cda2657b84 100644 (file)
--- a/verilog/lm32/lm32_dcache.v
+++ b/verilog/lm32/lm32_dcache.v
@@ -112,14 +112,14 @@ parameter bytes_per_line = 16;                          // Number of bytes per c
 parameter base_address = 0;                             // Base address of cachable memory
 parameter limit = 0;                                    // Limit (highest address) of cachable memory
 
-localparam addr_offset_width = $clog2(bytes_per_line)-2;
-localparam addr_set_width = $clog2(sets);
+localparam addr_offset_width = `CLOG2(bytes_per_line)-2;
+localparam addr_set_width = `CLOG2(sets);
 localparam addr_offset_lsb = 2;
 localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
 localparam addr_set_lsb = (addr_offset_msb+1);
 localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
 localparam addr_tag_lsb = (addr_set_msb+1);
-localparam addr_tag_msb = $clog2(`CFG_DCACHE_LIMIT-`CFG_DCACHE_BASE_ADDRESS);
+localparam addr_tag_msb = `CLOG2(`CFG_DCACHE_LIMIT-`CFG_DCACHE_BASE_ADDRESS);
 localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
 
 /////////////////////////////////////////////////////

diff --git a/verilog/lm32/lm32_icache.v b/verilog/lm32/lm32_icache.v
index 412ee9044a748ecfe1a67d9b049e90f2891b0780..b329d8e8aeb5073b5dbded444703738b1f5fc823 100644 (file)
--- a/verilog/lm32/lm32_icache.v
+++ b/verilog/lm32/lm32_icache.v
@@ -119,14 +119,14 @@ parameter bytes_per_line = 16;                          // Number of bytes per c
 parameter base_address = 0;                             // Base address of cachable memory
 parameter limit = 0;                                    // Limit (highest address) of cachable memory
 
-localparam addr_offset_width = $clog2(bytes_per_line)-2;
-localparam addr_set_width = $clog2(sets);
+localparam addr_offset_width = `CLOG2(bytes_per_line)-2;
+localparam addr_set_width = `CLOG2(sets);
 localparam addr_offset_lsb = 2;
 localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
 localparam addr_set_lsb = (addr_offset_msb+1);
 localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
 localparam addr_tag_lsb = (addr_set_msb+1);
-localparam addr_tag_msb = $clog2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS);
+localparam addr_tag_msb = `CLOG2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS);
 localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
 
 /////////////////////////////////////////////////////

diff --git a/verilog/lm32/lm32_instruction_unit.v b/verilog/lm32/lm32_instruction_unit.v
index 4f688c108bbf7d9ca1121569f31dbc9ad013aae8..2f5112d3d8e5b35a46fb70f9651f496a17819e00 100644 (file)
--- a/verilog/lm32/lm32_instruction_unit.v
+++ b/verilog/lm32/lm32_instruction_unit.v
@@ -179,7 +179,7 @@ parameter base_address = 0;                             // Base address of cacha
 parameter limit = 0;                                    // Limit (highest address) of cachable memory
 
 // For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used 
-localparam addr_offset_width = bytes_per_line == 4 ? 1 : $clog2(bytes_per_line)-2;
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : `CLOG2(bytes_per_line)-2;
 localparam addr_offset_lsb = 2;
 localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
 
@@ -388,18 +388,18 @@ reg alternate_eba_taken;
        // ----- Parameters -------
        .pmi_family             (`LATTICE_FAMILY),
         
-       //.pmi_addr_depth_a       (1 << $clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
-       //.pmi_addr_width_a       ($clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
+       //.pmi_addr_depth_a       (1 << `CLOG2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
+       //.pmi_addr_width_a       (`CLOG2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
        //.pmi_data_width_a       (`LM32_WORD_WIDTH),
-       //.pmi_addr_depth_b       (1 << $clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
-       //.pmi_addr_width_b       ($clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
+       //.pmi_addr_depth_b       (1 << `CLOG2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
+       //.pmi_addr_width_b       (`CLOG2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
        //.pmi_data_width_b       (`LM32_WORD_WIDTH),
         
        .pmi_addr_depth_a       (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1),
-       .pmi_addr_width_a       ($clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
+       .pmi_addr_width_a       (`CLOG2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
        .pmi_data_width_a       (`LM32_WORD_WIDTH),
        .pmi_addr_depth_b       (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1),
-       .pmi_addr_width_b       ($clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
+       .pmi_addr_width_b       (`CLOG2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
        .pmi_data_width_b       (`LM32_WORD_WIDTH),
         
        .pmi_regmode_a          ("noreg"),
@@ -418,8 +418,8 @@ reg alternate_eba_taken;
            .ResetB                 (rst_i),
            .DataInA                ({32{1'b0}}),
            .DataInB                (irom_store_data_m),
-           .AddressA               (pc_a[$clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]),
-           .AddressB               (irom_address_xm[$clog2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]),
+           .AddressA               (pc_a[`CLOG2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]),
+           .AddressB               (irom_address_xm[`CLOG2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)+2-1:2]),
            .ClockEnA               (!stall_a),
            .ClockEnB               (!stall_x || !stall_m),
            .WrA                    (`FALSE),

diff --git a/verilog/lm32/lm32_load_store_unit.v b/verilog/lm32/lm32_load_store_unit.v
index 088a69b5ff3c63ff5e521d15c7efbfaf89c71371..fcf9bc35ee966de36e2f9048c1f1acdc0059eb88 100644 (file)
--- a/verilog/lm32/lm32_load_store_unit.v
+++ b/verilog/lm32/lm32_load_store_unit.v
@@ -139,7 +139,7 @@ parameter base_address = 0;                             // Base address of cacha
 parameter limit = 0;                                    // Limit (highest address) of cachable memory
 
 // For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used 
-localparam addr_offset_width = bytes_per_line == 4 ? 1 : $clog2(bytes_per_line)-2;
+localparam addr_offset_width = bytes_per_line == 4 ? 1 : `CLOG2(bytes_per_line)-2;
 localparam addr_offset_lsb = 2;
 localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
 
@@ -293,18 +293,18 @@ reg wb_load_complete;                                   // Indicates when a Wish
        // ----- Parameters -------
        .pmi_family             (`LATTICE_FAMILY),
 
-       //.pmi_addr_depth_a       (1 << $clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
-       //.pmi_addr_width_a       ($clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
+       //.pmi_addr_depth_a       (1 << `CLOG2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
+       //.pmi_addr_width_a       (`CLOG2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
        //.pmi_data_width_a       (`LM32_WORD_WIDTH),
-       //.pmi_addr_depth_b       (1 << $clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
-       //.pmi_addr_width_b       ($clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
+       //.pmi_addr_depth_b       (1 << `CLOG2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
+       //.pmi_addr_width_b       (`CLOG2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
        //.pmi_data_width_b       (`LM32_WORD_WIDTH),
        
        .pmi_addr_depth_a       (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1),
-       .pmi_addr_width_a       ($clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
+       .pmi_addr_width_a       (`CLOG2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
        .pmi_data_width_a       (`LM32_WORD_WIDTH),
        .pmi_addr_depth_b       (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1),
-       .pmi_addr_width_b       ($clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
+       .pmi_addr_width_b       (`CLOG2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
        .pmi_data_width_b       (`LM32_WORD_WIDTH),
 
        .pmi_regmode_a          ("noreg"),
@@ -323,8 +323,8 @@ reg wb_load_complete;                                   // Indicates when a Wish
            .ResetB                 (rst_i),
            .DataInA                ({32{1'b0}}),
            .DataInB                (dram_store_data_m),
-           .AddressA               (load_store_address_x[$clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)+2-1:2]),
-           .AddressB               (load_store_address_m[$clog2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)+2-1:2]),
+           .AddressA               (load_store_address_x[`CLOG2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)+2-1:2]),
+           .AddressB               (load_store_address_m[`CLOG2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)+2-1:2]),
            // .ClockEnA               (!stall_x & (load_x | store_x)),
            .ClockEnA               (!stall_x),
            .ClockEnB               (!stall_m),