examples/corelogic_conv: use two dividers

diff --git a/examples/corelogic_conv.py b/examples/corelogic_conv.py
index 4bf058ff21737c2543b0e7f92962c770c47217ab..dd9c986b7c7a9740c9d185e61408376f652671c4 100644 (file)
--- a/examples/corelogic_conv.py
+++ b/examples/corelogic_conv.py
@@ -1,8 +1,10 @@
 from migen.fhdl import verilog
-from migen.corelogic import roundrobin, divider
+from migen.corelogic import divider
 
-r = roundrobin.Inst(5)
-d = divider.Inst(16)
-frag = r.get_fragment() + d.get_fragment()
-o = verilog.convert(frag, {r.request, r.grant, d.ready_o, d.quotient_o, d.remainder_o, d.start_i, d.dividend_i, d.divisor_i})
+d1 = divider.Inst(16)
+d2 = divider.Inst(16)
+frag = d1.get_fragment() + d2.get_fragment()
+o = verilog.convert(frag, {
+       d1.ready_o, d1.quotient_o, d1.remainder_o, d1.start_i, d1.dividend_i, d1.divisor_i,
+       d2.ready_o, d2.quotient_o, d2.remainder_o, d2.start_i, d2.dividend_i, d2.divisor_i})
 print(o)