cpu, arch: Replace the CCReg type with RegVal.

Most architectures weren't using the CCReg type, and in x86 and arm
it was already a uint64_t.

Change-Id: I0b3d5e690e6b31db6f2627f449c89bde0f6750a6
Reviewed-on: https://gem5-review.googlesource.com/c/14515
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh
index e2e8fedccf4c5597aed8cb0a8537c2c411cfd78e..d87d24575b05cc7159f9804ebf31426eb0e679f4 100644 (file)
--- a/src/arch/alpha/registers.hh
+++ b/src/arch/alpha/registers.hh
@@ -46,9 +46,6 @@ using AlphaISAInst::MaxInstDestRegs;
 // Locked read/write flags are can't be detected by the ISA parser
 const int MaxMiscDestRegs = AlphaISAInst::MaxMiscDestRegs + 1;
 
-// dummy typedef since we don't have CC regs
-typedef uint8_t CCReg;
-
 // Not applicable to Alpha
 using VecElem = ::DummyVecElem;
 using VecReg = ::DummyVecReg;

diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index 8960f9f929c13f82cb5b5fed2ecee245a1a44152..fd59f3ed81447d5bbcc760871a291012e80f3316 100644 (file)
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -77,9 +77,6 @@ using VecPredRegContainer = ::DummyVecPredRegContainer;
 constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
 constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
 
-// condition code register; must be at least 32 bits for FpCondCodes
-typedef uint64_t CCReg;
-
 // Constants Related to the number of registers
 const int NumIntArchRegs = NUM_ARCH_INTREGS;
 // The number of single precision floating point registers

diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index 702e486232ca0348ea469ad5f27b28fc7febe696..27536baeadfed8ef20f6277403291832172b2107 100644 (file)
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -283,9 +283,6 @@ const int NumMiscRegs = MISCREG_NUMREGS;
 
 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
 
-// dummy typedef since we don't have CC regs
-typedef uint8_t CCReg;
-
 // Not applicable to MIPS
 using VecElem = ::DummyVecElem;
 using VecReg = ::DummyVecReg;

diff --git a/src/arch/null/registers.hh b/src/arch/null/registers.hh
index 49ea4c79c4b01633525cf310d05379f419cbc29e..0ad0ea4bd3dce799af249379fb456dd8a3e47b77 100644 (file)
--- a/src/arch/null/registers.hh
+++ b/src/arch/null/registers.hh
@@ -47,7 +47,6 @@
 
 namespace NullISA {
 
-typedef uint8_t CCReg;
 const RegIndex ZeroReg = 0;
 
 // Not applicable to null

diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index 9d793d390f8a29e61421b71d275aa0d28d669b37..a494425cd1fe0e88e7072984d0aca48b007e7fd4 100644 (file)
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -46,9 +46,6 @@ using PowerISAInst::MaxInstDestRegs;
 // be detected by it. Manually add it here.
 const int MaxMiscDestRegs = PowerISAInst::MaxMiscDestRegs + 1;
 
-// dummy typedef since we don't have CC regs
-typedef uint8_t CCReg;
-
 // Not applicable to Power
 using VecElem = ::DummyVecElem;
 using VecReg = ::DummyVecReg;

diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index e2d1d154bd38b6b7369d89c1f40dbecb32b03ed3..c2e1fd2b5997f1e9e7e43e814eab9f70039589c4 100644 (file)
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -64,8 +64,6 @@ using RiscvISAInst::MaxInstSrcRegs;
 using RiscvISAInst::MaxInstDestRegs;
 const int MaxMiscDestRegs = 1;
 
-typedef uint8_t CCReg; // Not applicable to Riscv
-
 // Not applicable to RISC-V
 using VecElem = ::DummyVecElem;
 using VecReg = ::DummyVecReg;

diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh
index d9b182e7fa428d429225778723dfc5abccd5366d..0c11f66b267fc07d886f914b36aae8f9300fd7ca 100644 (file)
--- a/src/arch/sparc/registers.hh
+++ b/src/arch/sparc/registers.hh
@@ -46,9 +46,6 @@ using SparcISAInst::MaxInstSrcRegs;
 using SparcISAInst::MaxInstDestRegs;
 using SparcISAInst::MaxMiscDestRegs;
 
-// dummy typedef since we don't have CC regs
-typedef uint8_t CCReg;
-
 // Not applicable to SPARC
 using VecElem = ::DummyVecElem;
 using VecReg = ::DummyVecReg;

diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index ea75ec9074439bd8cd38b65830188f1c3a43df9a..0590abe49bb547d79fb03f2f1790486587e70202 100644 (file)
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -96,8 +96,6 @@ const int FramePointerReg = INTREG_RBP;
 // value
 const int SyscallPseudoReturnReg = INTREG_RDX;
 
-typedef uint64_t CCReg;
-
 // Not applicable to x86
 using VecElem = ::DummyVecElem;
 using VecReg = ::DummyVecReg;

diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index b87fd8b4ed483c82007980d483a92a5dbd9454a9..c24517937d4f5e00d775d9343b00a711bc47346d 100644 (file)
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -662,7 +662,7 @@ class BaseDynInst : public ExecContext, public RefCounted
     }
 
     /** Records a CC register being set to a value. */
-    void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
+    void setCCRegOperand(const StaticInst *si, int idx, RegVal val)
     {
         setScalarResult(val);
     }

diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 30d17bdf60357601f8cb794543e9d976659abede..e32c015bfe84e10f62731271265f5d9435ce3c81 100644 (file)
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -320,7 +320,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
         return thread->getWritableVecPredReg(reg);
     }
 
-    CCReg
+    RegVal
     readCCRegOperand(const StaticInst *si, int idx) override
     {
         const RegId& reg = si->srcRegIdx(idx);
@@ -379,7 +379,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
     }
 
     void
-    setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
+    setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
     {
         const RegId& reg = si->destRegIdx(idx);
         assert(reg.isCCReg());

diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index 99506c1c8dcc525c4279898211ea5ddb11206031..0983d03efe11131a980af73b653c3107d0ab2042 100644 (file)
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -269,7 +269,7 @@ class CheckerThreadContext : public ThreadContext
     VecPredRegContainer& getWritableVecPredReg(const RegId& reg) override
     { return actualTC->getWritableVecPredReg(reg); }
 
-    CCReg readCCReg(int reg_idx)
+    RegVal readCCReg(int reg_idx)
     { return actualTC->readCCReg(reg_idx); }
 
     void
@@ -308,7 +308,7 @@ class CheckerThreadContext : public ThreadContext
     }
 
     void
-    setCCReg(int reg_idx, CCReg val)
+    setCCReg(int reg_idx, RegVal val)
     {
         actualTC->setCCReg(reg_idx, val);
         checkerTC->setCCReg(reg_idx, val);
@@ -450,10 +450,10 @@ class CheckerThreadContext : public ThreadContext
     void setVecPredRegFlat(int idx, const VecPredRegContainer& val) override
     { actualTC->setVecPredRegFlat(idx, val); }
 
-    CCReg readCCRegFlat(int idx)
+    RegVal readCCRegFlat(int idx)
     { return actualTC->readCCRegFlat(idx); }
 
-    void setCCRegFlat(int idx, CCReg val)
+    void setCCRegFlat(int idx, RegVal val)
     { actualTC->setCCRegFlat(idx, val); }
 };
 

diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index 87af91623c23f3f3671ea59653a04bab17533452..1c1c8956a2f40b60bbbf4fc1e206028208672e5d 100644 (file)
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -74,7 +74,6 @@ class ExecContext {
   public:
     typedef TheISA::PCState PCState;
 
-    typedef TheISA::CCReg CCReg;
     using VecRegContainer = TheISA::VecRegContainer;
     using VecElem = TheISA::VecElem;
     using VecPredRegContainer = TheISA::VecPredRegContainer;
@@ -189,8 +188,9 @@ class ExecContext {
      * @{
      * @name Condition Code Registers
      */
-    virtual CCReg readCCRegOperand(const StaticInst *si, int idx) = 0;
-    virtual void setCCRegOperand(const StaticInst *si, int idx, CCReg val) = 0;
+    virtual RegVal readCCRegOperand(const StaticInst *si, int idx) = 0;
+    virtual void setCCRegOperand(
+            const StaticInst *si, int idx, RegVal val) = 0;
     /** @} */
 
     /**

diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 051cf412cbcc2e7759381e0baf869a402367556d..34bd71dfb054ff2c0800d5b666c4410ff8c3e291 100644 (file)
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -401,7 +401,7 @@ class ExecContext : public ::ExecContext
         thread.getDTBPtr()->demapPage(vaddr, asn);
     }
 
-    TheISA::CCReg
+    RegVal
     readCCRegOperand(const StaticInst *si, int idx) override
     {
         const RegId& reg = si->srcRegIdx(idx);
@@ -410,7 +410,7 @@ class ExecContext : public ::ExecContext
     }
 
     void
-    setCCRegOperand(const StaticInst *si, int idx, TheISA::CCReg val) override
+    setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
     {
         const RegId& reg = si->destRegIdx(idx);
         assert(reg.isCCReg());

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 0cea74861f5eeacb0a9a07e72720243a858eb573..f5aa9f71239bf161bc6440c0c00294a4064ca5af 100644 (file)
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1379,7 +1379,7 @@ FullO3CPU<Impl>::getWritableVecPredReg(PhysRegIdPtr phys_reg)
 }
 
 template <class Impl>
-CCReg
+RegVal
 FullO3CPU<Impl>::readCCReg(PhysRegIdPtr phys_reg)
 {
     ccRegfileReads++;
@@ -1429,7 +1429,7 @@ FullO3CPU<Impl>::setVecPredReg(PhysRegIdPtr phys_reg,
 
 template <class Impl>
 void
-FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, CCReg val)
+FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, RegVal val)
 {
     ccRegfileWrites++;
     regFile.setCCReg(phys_reg, val);
@@ -1508,7 +1508,7 @@ FullO3CPU<Impl>::getWritableArchVecPredReg(int reg_idx, ThreadID tid)
 }
 
 template <class Impl>
-CCReg
+RegVal
 FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
 {
     ccRegfileReads++;
@@ -1572,7 +1572,7 @@ FullO3CPU<Impl>::setArchVecPredReg(int reg_idx, const VecPredRegContainer& val,
 
 template <class Impl>
 void
-FullO3CPU<Impl>::setArchCCReg(int reg_idx, CCReg val, ThreadID tid)
+FullO3CPU<Impl>::setArchCCReg(int reg_idx, RegVal val, ThreadID tid)
 {
     ccRegfileWrites++;
     PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(

diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 9612b366772b9490a2403b9f976f21a9aca2a7bf..aabac5fead0422322f308f6deb0b96e8ad6c5258 100644 (file)
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -463,7 +463,7 @@ class FullO3CPU : public BaseO3CPU
 
     VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr reg_idx);
 
-    TheISA::CCReg readCCReg(PhysRegIdPtr phys_reg);
+    RegVal readCCReg(PhysRegIdPtr phys_reg);
 
     void setIntReg(PhysRegIdPtr phys_reg, RegVal val);
 
@@ -475,7 +475,7 @@ class FullO3CPU : public BaseO3CPU
 
     void setVecPredReg(PhysRegIdPtr reg_idx, const VecPredRegContainer& val);
 
-    void setCCReg(PhysRegIdPtr phys_reg, TheISA::CCReg val);
+    void setCCReg(PhysRegIdPtr phys_reg, RegVal val);
 
     RegVal readArchIntReg(int reg_idx, ThreadID tid);
 
@@ -514,7 +514,7 @@ class FullO3CPU : public BaseO3CPU
 
     VecPredRegContainer& getWritableArchVecPredReg(int reg_idx, ThreadID tid);
 
-    TheISA::CCReg readArchCCReg(int reg_idx, ThreadID tid);
+    RegVal readArchCCReg(int reg_idx, ThreadID tid);
 
     /** Architectural register accessors.  Looks up in the commit
      * rename table to obtain the true physical index of the
@@ -533,7 +533,7 @@ class FullO3CPU : public BaseO3CPU
     void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
                         const VecElem& val, ThreadID tid);
 
-    void setArchCCReg(int reg_idx, TheISA::CCReg val, ThreadID tid);
+    void setArchCCReg(int reg_idx, RegVal val, ThreadID tid);
 
     /** Sets the commit PC state of a specific thread. */
     void pcState(const TheISA::PCState &newPCState, ThreadID tid);

diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index e6dffc81d26bb4c9b5af0fbccfec5a1a7edb6c01..fc9abb92eee228f7f32e560fc49ab2386bf29231 100644 (file)
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -66,7 +66,6 @@ class BaseO3DynInst : public BaseDynInst<Impl>
     /** Binary machine instruction type. */
     typedef TheISA::MachInst MachInst;
     /** Register types. */
-    typedef TheISA::CCReg   CCReg;
     using VecRegContainer = TheISA::VecRegContainer;
     using VecElem = TheISA::VecElem;
     static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg;
@@ -378,7 +377,8 @@ class BaseO3DynInst : public BaseDynInst<Impl>
         return this->cpu->getWritableVecPredReg(this->_destRegIdx[idx]);
     }
 
-    CCReg readCCRegOperand(const StaticInst *si, int idx)
+    RegVal
+    readCCRegOperand(const StaticInst *si, int idx)
     {
         return this->cpu->readCCReg(this->_srcRegIdx[idx]);
     }
@@ -424,7 +424,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
         BaseDynInst<Impl>::setVecPredRegOperand(si, idx, val);
     }
 
-    void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
+    void setCCRegOperand(const StaticInst *si, int idx, RegVal val)
     {
         this->cpu->setCCReg(this->_destRegIdx[idx], val);
         BaseDynInst<Impl>::setCCRegOperand(si, idx, val);

diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 163a13a25373252d015548be08d8a3111022e1f7..d2fcd0749a41635b9af34eb43541563db7392e88 100644 (file)
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -65,7 +65,6 @@ class PhysRegFile
 {
   private:
 
-    typedef TheISA::CCReg CCReg;
     using VecElem = TheISA::VecElem;
     using VecRegContainer = TheISA::VecRegContainer;
     using PhysIds = std::vector<PhysRegId>;
@@ -95,7 +94,7 @@ class PhysRegFile
     std::vector<PhysRegId> vecPredRegIds;
 
     /** Condition-code register file. */
-    std::vector<CCReg> ccRegFile;
+    std::vector<RegVal> ccRegFile;
     std::vector<PhysRegId> ccRegIds;
 
     /** Misc Reg Ids */
@@ -290,7 +289,7 @@ class PhysRegFile
     }
 
     /** Reads a condition-code register. */
-    CCReg
+    RegVal
     readCCReg(PhysRegIdPtr phys_reg)
     {
         assert(phys_reg->isCCPhysReg());
@@ -365,7 +364,7 @@ class PhysRegFile
 
     /** Sets a condition-code register to the given value. */
     void
-    setCCReg(PhysRegIdPtr phys_reg, CCReg val)
+    setCCReg(PhysRegIdPtr phys_reg, RegVal val)
     {
         assert(phys_reg->isCCPhysReg());
 

diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 1ab1a08764558fd1281191b21fc1384f99d11b68..5a05c0200b17e91454e782f47021353cada86862 100644 (file)
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -271,7 +271,9 @@ class O3ThreadContext : public ThreadContext
         return getWritableVecPredRegFlat(flattenRegId(id).index());
     }
 
-    virtual CCReg readCCReg(int reg_idx) {
+    virtual RegVal
+    readCCReg(int reg_idx)
+    {
         return readCCRegFlat(flattenRegId(RegId(CCRegClass,
                                                  reg_idx)).index());
     }
@@ -310,7 +312,7 @@ class O3ThreadContext : public ThreadContext
     }
 
     virtual void
-    setCCReg(int reg_idx, CCReg val)
+    setCCReg(int reg_idx, RegVal val)
     {
         setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val);
     }
@@ -424,8 +426,8 @@ class O3ThreadContext : public ThreadContext
     virtual void setVecPredRegFlat(int idx,
                                    const VecPredRegContainer& val) override;
 
-    virtual CCReg readCCRegFlat(int idx);
-    virtual void setCCRegFlat(int idx, CCReg val);
+    virtual RegVal readCCRegFlat(int idx);
+    virtual void setCCRegFlat(int idx, RegVal val);
 };
 
 #endif

diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index 2f653fa04e89cd420ddecc38038fa09698933858..473e2e28ebb13b0ee4bdd548f7f01a80961e20c6 100644 (file)
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -247,7 +247,7 @@ O3ThreadContext<Impl>::getWritableVecPredRegFlat(int reg_id)
 }
 
 template <class Impl>
-TheISA::CCReg
+RegVal
 O3ThreadContext<Impl>::readCCRegFlat(int reg_idx)
 {
     return cpu->readArchCCReg(reg_idx, thread->threadId());
@@ -301,7 +301,7 @@ O3ThreadContext<Impl>::setVecPredRegFlat(int reg_idx,
 
 template <class Impl>
 void
-O3ThreadContext<Impl>::setCCRegFlat(int reg_idx, TheISA::CCReg val)
+O3ThreadContext<Impl>::setCCRegFlat(int reg_idx, RegVal val)
 {
     cpu->setArchCCReg(reg_idx, val, thread->threadId());
 

diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index 3090f38a09047db91a7fc0b4d114d39c175d77a4..0552dc0c63fb0f61b08fb97d54992152418ce38f 100644 (file)
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -60,7 +60,6 @@ class BaseSimpleCPU;
 
 class SimpleExecContext : public ExecContext {
   protected:
-    typedef TheISA::CCReg CCReg;
     using VecRegContainer = TheISA::VecRegContainer;
     using VecElem = TheISA::VecElem;
 
@@ -365,7 +364,7 @@ class SimpleExecContext : public ExecContext {
         thread->setVecPredReg(reg, val);
     }
 
-    CCReg
+    RegVal
     readCCRegOperand(const StaticInst *si, int idx) override
     {
         numCCRegReads++;
@@ -375,7 +374,7 @@ class SimpleExecContext : public ExecContext {
     }
 
     void
-    setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
+    setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
     {
         numCCRegWrites++;
         const RegId& reg = si->destRegIdx(idx);

diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 5c52ba28daaab5a8adb2545e30c7c4cb8872dd76..3dddc6768908b610484a6b1131e83c6c75c3942d 100644 (file)
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -100,7 +100,6 @@ class SimpleThread : public ThreadState
 {
   protected:
     typedef TheISA::MachInst MachInst;
-    typedef TheISA::CCReg CCReg;
     using VecRegContainer = TheISA::VecRegContainer;
     using VecElem = TheISA::VecElem;
     using VecPredRegContainer = TheISA::VecPredRegContainer;
@@ -113,7 +112,7 @@ class SimpleThread : public ThreadState
     VecRegContainer vecRegs[TheISA::NumVecRegs];
     VecPredRegContainer vecPredRegs[TheISA::NumVecPredRegs];
 #ifdef ISA_HAS_CC_REGS
-    TheISA::CCReg ccRegs[TheISA::NumCCRegs];
+    RegVal ccRegs[TheISA::NumCCRegs];
 #endif
     TheISA::ISA *const isa;    // one "instance" of the current ISA.
 
@@ -379,7 +378,8 @@ class SimpleThread : public ThreadState
         return regVal;
     }
 
-    CCReg readCCReg(int reg_idx)
+    RegVal
+    readCCReg(int reg_idx)
     {
 #ifdef ISA_HAS_CC_REGS
         int flatIndex = isa->flattenCCIndex(reg_idx);
@@ -449,7 +449,7 @@ class SimpleThread : public ThreadState
     }
 
     void
-    setCCReg(int reg_idx, CCReg val)
+    setCCReg(int reg_idx, RegVal val)
     {
 #ifdef ISA_HAS_CC_REGS
         int flatIndex = isa->flattenCCIndex(reg_idx);
@@ -622,13 +622,13 @@ class SimpleThread : public ThreadState
     }
 
 #ifdef ISA_HAS_CC_REGS
-    CCReg readCCRegFlat(int idx) { return ccRegs[idx]; }
-    void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; }
+    RegVal readCCRegFlat(int idx) { return ccRegs[idx]; }
+    void setCCRegFlat(int idx, RegVal val) { ccRegs[idx] = val; }
 #else
-    CCReg readCCRegFlat(int idx)
+    RegVal readCCRegFlat(int idx)
     { panic("readCCRegFlat w/no CC regs!\n"); }
 
-    void setCCRegFlat(int idx, CCReg val)
+    void setCCRegFlat(int idx, RegVal val)
     { panic("setCCRegFlat w/no CC regs!\n"); }
 #endif
 };

diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
index 3f5781b321b565164f6b88eea1657a900386e4a2..d122dd6127cde20a80d52b4a69196e6fcbe6be73 100644 (file)
--- a/src/cpu/thread_context.cc
+++ b/src/cpu/thread_context.cc
@@ -108,8 +108,8 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two)
 
     // loop through the Condition Code registers.
     for (int i = 0; i < TheISA::NumCCRegs; ++i) {
-        TheISA::CCReg t1 = one->readCCReg(i);
-        TheISA::CCReg t2 = two->readCCReg(i);
+        RegVal t1 = one->readCCReg(i);
+        RegVal t2 = two->readCCReg(i);
         if (t1 != t2)
             panic("CC reg idx %d doesn't match, one: %#x, two: %#x",
                   i, t1, t2);
@@ -192,7 +192,7 @@ serialize(ThreadContext &tc, CheckpointOut &cp)
     SERIALIZE_ARRAY(intRegs, NumIntRegs);
 
 #ifdef ISA_HAS_CC_REGS
-    CCReg ccRegs[NumCCRegs];
+    RegVal ccRegs[NumCCRegs];
     for (int i = 0; i < NumCCRegs; ++i)
         ccRegs[i] = tc.readCCRegFlat(i);
     SERIALIZE_ARRAY(ccRegs, NumCCRegs);
@@ -233,7 +233,7 @@ unserialize(ThreadContext &tc, CheckpointIn &cp)
         tc.setIntRegFlat(i, intRegs[i]);
 
 #ifdef ISA_HAS_CC_REGS
-    CCReg ccRegs[NumCCRegs];
+    RegVal ccRegs[NumCCRegs];
     UNSERIALIZE_ARRAY(ccRegs, NumCCRegs);
     for (int i = 0; i < NumCCRegs; ++i)
         tc.setCCRegFlat(i, ccRegs[i]);

diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 098fe3bb2c7d4ff6ffee1e13d1a5bccce5da0089..a570b9a00b66a8132f84475fa57d2cf3c9d1a902 100644 (file)
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -95,7 +95,6 @@ class ThreadContext
 {
   protected:
     typedef TheISA::MachInst MachInst;
-    typedef TheISA::CCReg CCReg;
     using VecRegContainer = TheISA::VecRegContainer;
     using VecElem = TheISA::VecElem;
     using VecPredRegContainer = TheISA::VecPredRegContainer;
@@ -248,7 +247,7 @@ class ThreadContext
         const = 0;
     virtual VecPredRegContainer& getWritableVecPredReg(const RegId& reg) = 0;
 
-    virtual CCReg readCCReg(int reg_idx) = 0;
+    virtual RegVal readCCReg(int reg_idx) = 0;
 
     virtual void setIntReg(int reg_idx, RegVal val) = 0;
 
@@ -261,7 +260,7 @@ class ThreadContext
     virtual void setVecPredReg(const RegId& reg,
                                const VecPredRegContainer& val) = 0;
 
-    virtual void setCCReg(int reg_idx, CCReg val) = 0;
+    virtual void setCCReg(int reg_idx, RegVal val) = 0;
 
     virtual TheISA::PCState pcState() = 0;
 
@@ -355,8 +354,8 @@ class ThreadContext
     virtual void setVecPredRegFlat(int idx,
                                    const VecPredRegContainer& val) = 0;
 
-    virtual CCReg readCCRegFlat(int idx) = 0;
-    virtual void setCCRegFlat(int idx, CCReg val) = 0;
+    virtual RegVal readCCRegFlat(int idx) = 0;
+    virtual void setCCRegFlat(int idx, RegVal val) = 0;
     /** @} */
 
 };
@@ -522,7 +521,7 @@ class ProxyThreadContext : public ThreadContext
     VecPredRegContainer& getWritableVecPredReg(const RegId& reg)
     { return actualTC->getWritableVecPredReg(reg); }
 
-    CCReg readCCReg(int reg_idx)
+    RegVal readCCReg(int reg_idx)
     { return actualTC->readCCReg(reg_idx); }
 
     void setIntReg(int reg_idx, RegVal val)
@@ -540,7 +539,7 @@ class ProxyThreadContext : public ThreadContext
     void setVecElem(const RegId& reg, const VecElem& val)
     { actualTC->setVecElem(reg, val); }
 
-    void setCCReg(int reg_idx, CCReg val)
+    void setCCReg(int reg_idx, RegVal val)
     { actualTC->setCCReg(reg_idx, val); }
 
     TheISA::PCState pcState() { return actualTC->pcState(); }
@@ -622,10 +621,10 @@ class ProxyThreadContext : public ThreadContext
     void setVecPredRegFlat(int idx, const VecPredRegContainer& val)
     { actualTC->setVecPredRegFlat(idx, val); }
 
-    CCReg readCCRegFlat(int idx)
+    RegVal readCCRegFlat(int idx)
     { return actualTC->readCCRegFlat(idx); }
 
-    void setCCRegFlat(int idx, CCReg val)
+    void setCCRegFlat(int idx, RegVal val)
     { actualTC->setCCRegFlat(idx, val); }
 };