i965: Switch TCS gl_program/gl_shader_program checks over to TES.

Tessellation control shaders are optional, but evaluation shaders will
always be present when using tessellation.  However, we'll always enable
the TCS (HS) hardware stage when using tessellation - we'll just create
a program on the fly.

That program, however, won't have a gl_program or gl_shader_program.
So we shouldn't check brw->tess_ctrl_program or
shader_prog->_LinkedShaders[MESA_SHADER_TESS_CTRL] - if we want to know
whether tessellation is enabled, we should look for a TES.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c
index ab765fb209a7311cd690b773431545ba6a893d5a..3095d82d91eeff8ce69a5ccd703fc982fc253bae 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -149,7 +149,7 @@ brw_codegen_vs_prog(struct brw_context *brw,
    brw_compute_vue_map(brw->intelScreen->devinfo,
                        &prog_data.base.vue_map, outputs_written,
                        prog ? prog->SeparateShader ||
-                              prog->_LinkedShaders[MESA_SHADER_TESS_CTRL]
+                              prog->_LinkedShaders[MESA_SHADER_TESS_EVAL]
                             : false);
 
    if (0) {

diff --git a/src/mesa/drivers/dri/i965/gen7_hs_state.c b/src/mesa/drivers/dri/i965/gen7_hs_state.c
index 97eb8d41e18d82103fb224e88ef63a880859e265..63b185e329ebd38ccc04d99762a0fa3277577dc6 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_hs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_hs_state.c
@@ -33,15 +33,16 @@ gen7_upload_tcs_push_constants(struct brw_context *brw)
    /* BRW_NEW_TESS_PROGRAMS */
    const struct brw_tess_ctrl_program *tcp =
       (struct brw_tess_ctrl_program *) brw->tess_ctrl_program;
+   bool active = brw->tess_eval_program;
 
-   if (tcp) {
+   if (active) {
       /* BRW_NEW_TCS_PROG_DATA */
       const struct brw_stage_prog_data *prog_data = &brw->tcs.prog_data->base.base;
       gen6_upload_push_constants(brw, &tcp->program.Base, prog_data,
                                       stage_state, AUB_TRACE_VS_CONSTANTS);
    }
 
-   gen7_upload_constant_state(brw, stage_state, tcp, _3DSTATE_CONSTANT_HS);
+   gen7_upload_constant_state(brw, stage_state, active, _3DSTATE_CONSTANT_HS);
 }
 
 const struct brw_tracked_state gen7_tcs_push_constants = {

diff --git a/src/mesa/drivers/dri/i965/gen8_hs_state.c b/src/mesa/drivers/dri/i965/gen8_hs_state.c
index b12f99ec035ffcf652762a9847265063d2ffc28f..21f3d4695534c05c0a6ed6b5e2249edaaa239a9f 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen8_hs_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_hs_state.c
@@ -31,7 +31,7 @@ gen8_upload_hs_state(struct brw_context *brw)
 {
    const struct brw_stage_state *stage_state = &brw->tcs.base;
    /* BRW_NEW_TESS_PROGRAMS */
-   bool active = brw->tess_ctrl_program;
+   bool active = brw->tess_eval_program;
    /* BRW_NEW_HS_PROG_DATA */
    const struct brw_vue_prog_data *prog_data = &brw->tcs.prog_data->base;