X86: Add support for x86 psrldq and pslldq instructions

These are complicated instructions and the micro-code might be suboptimal.

This has been tested with some small sample programs (attached)

The psrldq instruction is needed by various spec2k programs.

diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index d52dfb26e951d13172affa8b3d292b8fd4b2eb85..288c5e5a866db21fd27201d9f9ffb3a670faef1c 100644 (file)
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -673,9 +673,9 @@
                         //0x3: group14_pshimq();
                         0x3: decode MODRM_REG {
                             0x2: PSRLQ(VRo,Ib);
-                            0x3: WarnUnimpl::psrldq_VRo_Ib();
+                            0x3: PSRLDQ(VRo,Ib);
                             0x6: PSLLQ(VRo,Ib);
-                            0x7: WarnUnimpl::pslldq_VRo_Ib();
+                            0x7: PSLLDQ(VRo,Ib);
                             default: UD2();
                         }
                         0x4: PCMPEQB(Vo,Wo);

diff --git a/src/arch/x86/isa/insts/simd128/integer/shift/left_logical_shift.py b/src/arch/x86/isa/insts/simd128/integer/shift/left_logical_shift.py
index 617033bc032f7347e043862ac35dc1f9da1b7b2f..c13c7064c31112396e47313f53952e68f2a76235 100644 (file)
--- a/src/arch/x86/isa/insts/simd128/integer/shift/left_logical_shift.py
+++ b/src/arch/x86/isa/insts/simd128/integer/shift/left_logical_shift.py
@@ -122,5 +122,43 @@ def macroop PSLLQ_XMM_I {
     mslli xmml, xmml, imm, size=8, ext=0
     mslli xmmh, xmmh, imm, size=8, ext=0
 };
+
+def macroop PSLLDQ_XMM_I {
+
+    limm  t2, 8
+    subi t1, t2, imm, flags=(ECF,), dataSize=1
+    br label("pslldq_less_8"), flags=(nCECF,)
+
+    # Greater than 8
+
+    limm  t2, 16
+    subi t1, t2, imm, flags=(ECF,), dataSize=1
+    br label("pslldq_less_16"), flags=(nCECF,)
+
+    # Greater than 16
+
+    lfpimm  xmml, 0
+    lfpimm  xmmh, 0
+    br label("pslldq_end")
+
+pslldq_less_16:
+
+    # Between 8 and 16
+
+    mslli xmmh, xmml, "(IMMEDIATE-8)<<3", size=8, ext=0
+    lfpimm  xmml, 0
+    br label("pslldq_end")
+
+pslldq_less_8:
+
+    # Less than 8
+
+    msrli ufp1, xmml, "(8-IMMEDIATE) << 3", size=8, ext=0
+    mslli xmmh, xmmh, "IMMEDIATE << 3", size=8, ext=0
+    mslli xmml, xmml, "IMMEDIATE << 3", size=8, ext=0
+    mor   xmmh, xmmh, ufp1
+
+pslldq_end:
+    fault "NoFault"
+};
 '''
-# PSLLDQ

diff --git a/src/arch/x86/isa/insts/simd128/integer/shift/right_logical_shift.py b/src/arch/x86/isa/insts/simd128/integer/shift/right_logical_shift.py
index c904eaf50f2b577be172358baf3dce01b3f99047..61efe1a5dd0d3fd1a653241a25ace2e82e9f6869 100644 (file)
--- a/src/arch/x86/isa/insts/simd128/integer/shift/right_logical_shift.py
+++ b/src/arch/x86/isa/insts/simd128/integer/shift/right_logical_shift.py
@@ -122,5 +122,41 @@ def macroop PSRLQ_XMM_I {
     msrli xmml, xmml, imm, size=8, ext=0
     msrli xmmh, xmmh, imm, size=8, ext=0
 };
+
+def macroop PSRLDQ_XMM_I {
+    limm  t2, 8
+    subi t1, t2, imm, flags=(ECF,), dataSize=1
+    br label("psrldq_less_8"), flags=(nCECF,)
+    # Greater than 8
+
+    limm  t2, 16
+    subi t1, t2, imm, flags=(ECF,), dataSize=1
+    br label("psrldq_less_16"), flags=(nCECF,)
+
+    # Greater than 16
+
+    lfpimm  xmml, 0
+    lfpimm  xmmh, 0
+    br label("psrldq_end")
+
+psrldq_less_16:
+
+    # Between 8 and 16
+
+    msrli xmml, xmmh, "(IMMEDIATE-8)<<3", size=8, ext=0
+    lfpimm  xmmh, 0
+    br label("psrldq_end")
+
+psrldq_less_8:
+
+    # Less than 8
+
+    mslli ufp1, xmmh, "(8-IMMEDIATE) << 3", size=8, ext=0
+    msrli xmml, xmml, "IMMEDIATE << 3", size=8, ext=0
+    msrli xmmh, xmmh, "IMMEDIATE << 3", size=8, ext=0
+    mor   xmml, xmml, ufp1
+
+psrldq_end:
+    fault "NoFault"
+};
 '''
-# PSRLDQ