cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
- physMemPort = system.physmem.port,
- physmem = system.physmem,
ruby_system = ruby_system)
l1_cntrl.sequencer = cpu_seq
# Create the Ruby objects associated with the dma controller
#
dma_seq = DMASequencer(version = i,
- physMemPort = system.physmem.port,
- physmem = system.physmem,
ruby_system = ruby_system)
dma_cntrl = DMA_Controller(version = i,
cpu_seq = RubySequencer(version = i,
icache = cache,
dcache = cache,
- physMemPort = system.physmem.port,
- physmem = system.physmem,
ruby_system = ruby_system)
l1_cntrl.sequencer = cpu_seq
# Create the Ruby objects associated with the dma controller
#
dma_seq = DMASequencer(version = i,
- physMemPort = system.physmem.port,
- physmem = system.physmem,
ruby_system = ruby_system)
dma_cntrl = DMA_Controller(version = i,
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
- physMemPort = system.physmem.port,
- physmem = system.physmem,
ruby_system = ruby_system)
l1_cntrl.sequencer = cpu_seq
# Create the Ruby objects associated with the dma controller
#
dma_seq = DMASequencer(version = i,
- physMemPort = system.physmem.port,
- physmem = system.physmem,
ruby_system = ruby_system)
dma_cntrl = DMA_Controller(version = i,
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
- physMemPort = system.physmem.port,
- physmem = system.physmem,
ruby_system = ruby_system)
l1_cntrl.sequencer = cpu_seq
# Create the Ruby objects associated with the dma controller
#
dma_seq = DMASequencer(version = i,
- physMemPort = system.physmem.port,
- physmem = system.physmem,
ruby_system = ruby_system)
dma_cntrl = DMA_Controller(version = i,
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
- physMemPort = system.physmem.port,
- physmem = system.physmem,
ruby_system = ruby_system)
l1_cntrl.sequencer = cpu_seq
# Create the Ruby objects associated with the dma controller
#
dma_seq = DMASequencer(version = i,
- physMemPort = system.physmem.port,
- physmem = system.physmem,
ruby_system = ruby_system)
dma_cntrl = DMA_Controller(version = i,
cpu_seq = RubySequencer(icache = cache,
dcache = cache,
- physMemPort = system.physmem.port,
- physmem = system.physmem,
using_network_tester = True,
ruby_system = ruby_system)
# Create a port proxy for connecting the system port. This is
# independent of the protocol and kept in the protocol-agnostic
# part (i.e. here).
- sys_port_proxy = RubyPortProxy(version = 0,
- physMemPort = system.physmem.port,
- physmem = system.physmem,
- ruby_system = ruby)
+ sys_port_proxy = RubyPortProxy(ruby_system = ruby)
# Give the system port proxy a SimObject parent without creating a
# full-fledged controller
system.sys_port_proxy = sys_port_proxy
void
PhysicalMemory::init()
{
- if (ports.empty()) {
- fatal("PhysicalMemory object %s is unconnected!", name());
- }
-
- for (PortIterator pi = ports.begin(); pi != ports.end(); ++pi) {
- (*pi)->sendRangeChange();
+ for (PortIterator p = ports.begin(); p != ports.end(); ++p) {
+ if (!(*p)->isConnected()) {
+ fatal("PhysicalMemory port %s is unconnected!\n", (*p)->name());
+ } else {
+ (*p)->sendRangeChange();
+ }
}
}
void virtual init();
unsigned int drain(Event *de);
- protected:
Tick doAtomicAccess(PacketPtr pkt);
void doFunctionalAccess(PacketPtr pkt);
+
+
+ protected:
virtual Tick calculateLatency(PacketPtr pkt);
public:
#include "mem/protocol/AccessPermission.hh"
#include "mem/ruby/slicc_interface/AbstractController.hh"
#include "mem/ruby/system/RubyPort.hh"
+#include "sim/system.hh"
RubyPort::RubyPort(const Params *p)
: MemObject(p), m_version(p->version), m_controller(NULL),
m_mandatory_q_ptr(NULL),
pio_port(csprintf("%s-pio-port", name()), this),
m_usingRubyTester(p->using_ruby_tester), m_request_cnt(0),
- physMemPort(csprintf("%s-physMemPort", name()), this),
- drainEvent(NULL), physmem(p->physmem), ruby_system(p->ruby_system),
+ drainEvent(NULL), ruby_system(p->ruby_system), system(p->system),
waitingOnSequencer(false), access_phys_mem(p->access_phys_mem)
{
assert(m_version != -1);
return pio_port;
}
- if (if_name == "physMemPort") {
- return physMemPort;
- }
-
// used by the x86 CPUs to connect the interrupt PIO and interrupt slave
// port
if (if_name != "master") {
// The following command performs the real functional access.
// This line should be removed once Ruby supplies the official version
// of data.
- ruby_port->physMemPort.sendFunctional(pkt);
+ ruby_port->system->physmem->doFunctionalAccess(pkt);
}
// turn packet around to go back to requester if response expected
count += pio_port.drain(de);
DPRINTF(Config, "count after pio check %d\n", count);
}
- if (physMemPort.isConnected()) {
- count += physMemPort.drain(de);
- DPRINTF(Config, "count after physmem check %d\n", count);
- }
for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) {
count += (*p)->drain(de);
DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse);
if (accessPhysMem) {
- ruby_port->physMemPort.sendAtomic(pkt);
+ ruby_port->system->physmem->doAtomicAccess(pkt);
} else if (needsResponse) {
pkt->makeResponse();
}
bool
RubyPort::M5Port::isPhysMemAddress(Addr addr)
{
- AddrRangeList physMemAddrList =
- ruby_port->physMemPort.getSlavePort().getAddrRanges();
- for (AddrRangeIter iter = physMemAddrList.begin();
- iter != physMemAddrList.end();
- iter++) {
- if (addr >= iter->start && addr <= iter->end) {
- DPRINTF(RubyPort, "Request found in %#llx - %#llx range\n",
- iter->start, iter->end);
- return true;
- }
- }
- return false;
+ return ruby_port->system->isMemory(addr);
}
unsigned
uint16_t m_port_id;
uint64_t m_request_cnt;
- PioPort physMemPort;
-
/** Vector of M5 Ports attached to this Ruby port. */
typedef std::vector<M5Port*>::iterator CpuPortIter;
std::vector<M5Port*> slave_ports;
Event *drainEvent;
- PhysicalMemory* physmem;
RubySystem* ruby_system;
+ System* system;
//
// Based on similar code in the M5 bus. Stores pointers to those ports
master = VectorMasterPort("CPU master port")
version = Param.Int(0, "")
pio_port = MasterPort("Ruby_pio_port")
- physmem = Param.PhysicalMemory("")
- physMemPort = MasterPort("port to physical memory")
using_ruby_tester = Param.Bool(False, "")
using_network_tester = Param.Bool(False, "")
access_phys_mem = Param.Bool(True,
"should the rubyport atomically update phys_mem")
ruby_system = Param.RubySystem("")
+ system = Param.System(Parent.any, "system object")
class RubyPortProxy(RubyPort):
type = 'RubyPortProxy'
projects / gem5.git / commitdiff