class BaseCPU(SimObject):
type = 'BaseCPU'
abstract = True
- mem = Param.PhysicalMemory(Parent.any, "memory")
+ mem = Param.MemObject("memory")
system = Param.System(Parent.any, "system object")
if build_env['FULL_SYSTEM']:
---------- Begin Simulation Statistics ----------
-host_inst_rate 2486 # Simulator instruction rate (inst/s)
-host_mem_usage 146652 # Number of bytes of host memory used
-host_seconds 1.04 # Real time elapsed on the host
-host_tick_rate 2484 # Simulator tick rate (ticks/s)
+host_inst_rate 58510 # Simulator instruction rate (inst/s)
+host_mem_usage 146720 # Number of bytes of host memory used
+host_seconds 0.04 # Real time elapsed on the host
+host_tick_rate 57971 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2578 # Number of instructions simulated
sim_seconds 0.000000 # Number of seconds simulated
All Rights Reserved
-M5 compiled Aug 16 2006 13:05:10
-M5 started Wed Aug 16 14:41:52 2006
+M5 compiled Aug 18 2006 00:06:43
+M5 started Fri Aug 18 00:12:48 2006
M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/test/opt/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic tests/run.py quick/00.hello/alpha/linux/simple-atomic
Exiting @ tick 2577 because target called exit()
[system.cpu]
type=TimingSimpleCPU
-children=workload
+children=dcache icache l2cache toL2Bus workload
clock=1
defer_registration=false
function_trace=false
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.physmem
+mem=system.cpu.dcache
system=system
workload=system.cpu.workload
+[system.cpu.dcache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+do_copy=false
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=262144
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+
+[system.cpu.icache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+do_copy=false
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=131072
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+
+[system.cpu.l2cache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+do_copy=false
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=2097152
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+
[system.cpu.workload]
type=LiveProcess
cmd=hello
type=PhysicalMemory
file=
latency=1
+range=0:134217727
[trace]
bufsize=0
[system.physmem]
type=PhysicalMemory
file=
-// range not specified
+range=[0,134217727]
latency=1
[system]
type=Bus
bus_id=0
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
[system.cpu.workload]
type=LiveProcess
cmd=hello
max_insts_all_threads=0
max_loads_any_thread=0
max_loads_all_threads=0
-mem=system.physmem
+mem=system.cpu.dcache
system=system
workload=system.cpu.workload
clock=1
function_trace_start=0
// simulate_stalls not specified
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+
+[system.cpu.icache]
+type=BaseCache
+size=131072
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.l2cache]
+type=BaseCache
+size=2097152
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
[trace]
flags=
start=0
---------- Begin Simulation Statistics ----------
-host_inst_rate 57948 # Simulator instruction rate (inst/s)
-host_mem_usage 146660 # Number of bytes of host memory used
-host_seconds 0.04 # Real time elapsed on the host
-host_tick_rate 73225 # Simulator tick rate (ticks/s)
+host_inst_rate 39478 # Simulator instruction rate (inst/s)
+host_mem_usage 158176 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
+host_tick_rate 57469 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2578 # Number of instructions simulated
sim_seconds 0.000000 # Number of seconds simulated
-sim_ticks 3287 # Number of ticks simulated
+sim_ticks 3777 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 416 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 2918912699678311424 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 361 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 160540198482307121152 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.132212 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 110 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.132212 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 4476343852030456320 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 267 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 120861284004822319104 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.091837 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 27 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 54 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.091837 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 27 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 7.658537 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 710 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 3431725396184505344 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 628 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 281401482487129440256 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.115493 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 82 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 164 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.115493 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 82 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 710 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 3431725396184505344 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 628 # number of overall hits
+system.cpu.dcache.overall_miss_latency 281401482487129440256 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.115493 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 82 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 164 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.115493 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 82 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 53.009529 # Cycle average of tags in use
+system.cpu.dcache.total_refs 628 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 0 # number of writebacks
+system.cpu.icache.ReadReq_accesses 2579 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 3447887748754160128 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 2416 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 562005703046928072704 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.063203 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 326 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.063203 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 14.822086 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 2579 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 3447887748754160128 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency
+system.cpu.icache.demand_hits 2416 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 562005703046928072704 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.063203 # miss rate for demand accesses
+system.cpu.icache.demand_misses 163 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 326 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.063203 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 2579 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 3447887748754160128 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 2416 # number of overall hits
+system.cpu.icache.overall_miss_latency 562005703046928072704 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.063203 # miss rate for overall accesses
+system.cpu.icache.overall_misses 163 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 326 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.063203 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 0 # number of replacements
+system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 93.126257 # Cycle average of tags in use
+system.cpu.icache.total_refs 2416 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.l2cache.ReadReq_accesses 245 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 2 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_miss_latency 490 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 245 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 245 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 245 # number of ReadReq MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 2 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 490 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 245 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 245 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 2 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 0 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 490 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 245 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 245 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.sampled_refs 245 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 146.200635 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 0 # number of cpu cycles simulated
system.cpu.num_insts 2578 # Number of instructions executed
All Rights Reserved
-M5 compiled Aug 16 2006 17:47:32
-M5 started Wed Aug 16 18:40:03 2006
+M5 compiled Aug 18 2006 00:06:43
+M5 started Fri Aug 18 00:12:48 2006
M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/test/opt/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing
-Exiting @ tick 3287 because target called exit()
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing
+Exiting @ tick 3777 because target called exit()
type=PhysicalMemory
file=
latency=1
+range=0:134217727
[trace]
bufsize=0
[system.physmem]
type=PhysicalMemory
file=
-// range not specified
+range=[0,134217727]
latency=1
[system]
---------- Begin Simulation Statistics ----------
-host_inst_rate 199422 # Simulator instruction rate (inst/s)
-host_mem_usage 147292 # Number of bytes of host memory used
-host_seconds 0.03 # Real time elapsed on the host
-host_tick_rate 196594 # Simulator tick rate (ticks/s)
+host_inst_rate 124620 # Simulator instruction rate (inst/s)
+host_mem_usage 147356 # Number of bytes of host memory used
+host_seconds 0.05 # Real time elapsed on the host
+host_tick_rate 122794 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5657 # Number of instructions simulated
sim_seconds 0.000000 # Number of seconds simulated
All Rights Reserved
-M5 compiled Aug 16 2006 18:15:37
-M5 started Wed Aug 16 18:33:21 2006
+M5 compiled Aug 18 2006 00:09:15
+M5 started Fri Aug 18 00:12:56 2006
M5 executing on zizzer.eecs.umich.edu
-command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/test/opt/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic
+command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic tests/run.py quick/00.hello/mips/linux/simple-atomic
Exiting @ tick 5656 because target called exit()
[system.cpu]
type=TimingSimpleCPU
-children=workload
+children=dcache icache l2cache toL2Bus workload
clock=1
defer_registration=false
function_trace=false
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.physmem
+mem=system.cpu.dcache
system=system
workload=system.cpu.workload
+[system.cpu.dcache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+do_copy=false
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=262144
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+
+[system.cpu.icache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+do_copy=false
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=131072
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+
+[system.cpu.l2cache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+do_copy=false
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=2097152
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+
[system.cpu.workload]
type=LiveProcess
cmd=hello
type=PhysicalMemory
file=
latency=1
+range=0:134217727
[trace]
bufsize=0
[system.physmem]
type=PhysicalMemory
file=
-// range not specified
+range=[0,134217727]
latency=1
[system]
type=Bus
bus_id=0
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
[system.cpu.workload]
type=LiveProcess
cmd=hello
max_insts_all_threads=0
max_loads_any_thread=0
max_loads_all_threads=0
-mem=system.physmem
+mem=system.cpu.dcache
system=system
workload=system.cpu.workload
clock=1
function_trace_start=0
// simulate_stalls not specified
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+
+[system.cpu.icache]
+type=BaseCache
+size=131072
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.l2cache]
+type=BaseCache
+size=2097152
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
[trace]
flags=
start=0
---------- Begin Simulation Statistics ----------
-host_inst_rate 45259 # Simulator instruction rate (inst/s)
-host_mem_usage 147292 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
-host_tick_rate 61490 # Simulator tick rate (ticks/s)
+host_inst_rate 67697 # Simulator instruction rate (inst/s)
+host_mem_usage 158936 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
+host_tick_rate 102046 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5657 # Number of instructions simulated
sim_seconds 0.000000 # Number of seconds simulated
-sim_ticks 7711 # Number of ticks simulated
+sim_ticks 8573 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 1131 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 1791574296802328064 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 1052 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 141534369447383908352 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.069850 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 79 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 158 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.069850 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 79 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 933 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 2766176443076198912 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 875 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 160438233698419539968 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.062165 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 58 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 100 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.053591 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 50 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 14.065693 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 2064 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 2204179585005864704 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 1927 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 301972603145803464704 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.066376 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 137 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 258 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.062500 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 129 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 2064 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 2204179585005864704 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 1927 # number of overall hits
+system.cpu.dcache.overall_miss_latency 301972603145803464704 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.066376 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 137 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 258 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.062500 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 129 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.sampled_refs 137 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 91.822487 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1927 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 0 # number of writebacks
+system.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 1549898021785231104 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 1.993399 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 5355 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 469619100600925028352 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.053552 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 604 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 17.673267 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 5658 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 1549898021785231104 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 1.993399 # average overall mshr miss latency
+system.cpu.icache.demand_hits 5355 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 469619100600925028352 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.053552 # miss rate for demand accesses
+system.cpu.icache.demand_misses 303 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 604 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.053552 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 5658 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 1549898021785231104 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 1.993399 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 5355 # number of overall hits
+system.cpu.icache.overall_miss_latency 469619100600925028352 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.053552 # miss rate for overall accesses
+system.cpu.icache.overall_misses 303 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 604 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.053552 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 13 # number of replacements
+system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 138.188010 # Cycle average of tags in use
+system.cpu.icache.total_refs 5355 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.l2cache.ReadReq_accesses 440 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 1.963470 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 860 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.995455 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 438 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 430 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.977273 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 430 # number of ReadReq MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0.004566 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 440 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 1.963470 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 860 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.995455 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 438 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 430 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.977273 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 430 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 440 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 1.963470 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 2 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 860 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.995455 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 438 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 430 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.977273 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 430 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.sampled_refs 438 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 231.300093 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 0 # number of cpu cycles simulated
system.cpu.num_insts 5657 # Number of instructions executed
All Rights Reserved
-M5 compiled Aug 16 2006 18:15:37
-M5 started Wed Aug 16 18:40:06 2006
+M5 compiled Aug 18 2006 00:09:15
+M5 started Fri Aug 18 00:12:56 2006
M5 executing on zizzer.eecs.umich.edu
-command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/test/opt/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing
-Exiting @ tick 7711 because target called exit()
+command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing
+Exiting @ tick 8573 because target called exit()
type=PhysicalMemory
file=
latency=1
+range=0:134217727
[trace]
bufsize=0
[system.physmem]
type=PhysicalMemory
file=
-// range not specified
+range=[0,134217727]
latency=1
[system]
---------- Begin Simulation Statistics ----------
-host_inst_rate 94707 # Simulator instruction rate (inst/s)
-host_mem_usage 147208 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
-host_tick_rate 93873 # Simulator tick rate (ticks/s)
+host_inst_rate 73574 # Simulator instruction rate (inst/s)
+host_mem_usage 147268 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
+host_tick_rate 73065 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 4450 # Number of instructions simulated
sim_seconds 0.000000 # Number of seconds simulated
All Rights Reserved
-M5 compiled Aug 16 2006 18:18:07
-M5 started Wed Aug 16 18:32:47 2006
+M5 compiled Aug 18 2006 00:11:48
+M5 started Fri Aug 18 00:12:59 2006
M5 executing on zizzer.eecs.umich.edu
-command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/test/opt/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic
+command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-atomic tests/run.py quick/00.hello/sparc/linux/simple-atomic
Exiting @ tick 4449 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 1386533 # Simulator instruction rate (inst/s)
-host_mem_usage 194484 # Number of bytes of host memory used
-host_seconds 45.63 # Real time elapsed on the host
-host_tick_rate 77934911 # Simulator tick rate (ticks/s)
+host_inst_rate 1433278 # Simulator instruction rate (inst/s)
+host_mem_usage 194568 # Number of bytes of host memory used
+host_seconds 44.14 # Real time elapsed on the host
+host_tick_rate 80562367 # Simulator tick rate (ticks/s)
sim_freq 2000000000 # Frequency of simulated ticks
sim_insts 63264995 # Number of instructions simulated
sim_seconds 1.778030 # Number of seconds simulated
All Rights Reserved
-M5 compiled Aug 16 2006 13:33:58
-M5 started Wed Aug 16 14:38:40 2006
+M5 compiled Aug 17 2006 23:41:21
+M5 started Thu Aug 17 23:50:27 2006
M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/test/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
+command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
Exiting @ tick 3556060806 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-host_inst_rate 1410348 # Simulator instruction rate (inst/s)
-host_mem_usage 194320 # Number of bytes of host memory used
-host_seconds 42.49 # Real time elapsed on the host
-host_tick_rate 82214431 # Simulator tick rate (ticks/s)
+host_inst_rate 1371456 # Simulator instruction rate (inst/s)
+host_mem_usage 194364 # Number of bytes of host memory used
+host_seconds 43.70 # Real time elapsed on the host
+host_tick_rate 79947218 # Simulator tick rate (ticks/s)
sim_freq 2000000000 # Frequency of simulated ticks
sim_insts 59929520 # Number of instructions simulated
sim_seconds 1.746773 # Number of seconds simulated
system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post
system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post
system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedTxIdle no value # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
0: system.tsunami.io.rtc: Real-time clock set to Sun Jan 1 00:00:00 2006
-Listening for console connection on port 3457
-0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001
+Listening for console connection on port 3456
+0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
warn: Entering event queue @ 0. Starting simulation...
All Rights Reserved
-M5 compiled Aug 16 2006 13:33:58
-M5 started Wed Aug 16 14:37:55 2006
+M5 compiled Aug 17 2006 23:41:21
+M5 started Thu Aug 17 23:41:25 2006
M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/test/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
+command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
Exiting @ tick 3493545624 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-host_inst_rate 868070 # Simulator instruction rate (inst/s)
-host_mem_usage 194536 # Number of bytes of host memory used
-host_seconds 72.68 # Real time elapsed on the host
-host_tick_rate 48701109 # Simulator tick rate (ticks/s)
+host_inst_rate 845052 # Simulator instruction rate (inst/s)
+host_mem_usage 194484 # Number of bytes of host memory used
+host_seconds 74.66 # Real time elapsed on the host
+host_tick_rate 47409778 # Simulator tick rate (ticks/s)
sim_freq 2000000000 # Frequency of simulated ticks
sim_insts 63088076 # Number of instructions simulated
sim_seconds 1.769718 # Number of seconds simulated
All Rights Reserved
-M5 compiled Aug 16 2006 13:33:58
-M5 started Wed Aug 16 14:40:36 2006
+M5 compiled Aug 17 2006 23:41:21
+M5 started Thu Aug 17 23:51:44 2006
M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/test/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
+command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
Exiting @ tick 3539435029 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-host_inst_rate 864969 # Simulator instruction rate (inst/s)
-host_mem_usage 194104 # Number of bytes of host memory used
-host_seconds 69.27 # Real time elapsed on the host
-host_tick_rate 50617416 # Simulator tick rate (ticks/s)
+host_inst_rate 859270 # Simulator instruction rate (inst/s)
+host_mem_usage 194168 # Number of bytes of host memory used
+host_seconds 69.73 # Real time elapsed on the host
+host_tick_rate 50283954 # Simulator tick rate (ticks/s)
sim_freq 2000000000 # Frequency of simulated ticks
sim_insts 59915182 # Number of instructions simulated
sim_seconds 1.753109 # Number of seconds simulated
system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post
system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post
system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post
-system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post
+system.tsunami.ethernet.coalescedTxIdle no value # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
0: system.tsunami.io.rtc: Real-time clock set to Sun Jan 1 00:00:00 2006
-Listening for console connection on port 3456
-0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
+Listening for console connection on port 3457
+0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001
warn: Entering event queue @ 0. Starting simulation...
All Rights Reserved
-M5 compiled Aug 16 2006 13:33:58
-M5 started Wed Aug 16 14:39:26 2006
+M5 compiled Aug 17 2006 23:41:21
+M5 started Thu Aug 17 23:41:25 2006
M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/test/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing
+command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing
Exiting @ tick 3506218170 because m5_exit instruction encountered
type=PhysicalMemory
file=
latency=1
+range=0:134217727
[trace]
bufsize=0
[system.physmem]
type=PhysicalMemory
file=
-// range not specified
+range=[0,134217727]
latency=1
[system]
---------- Begin Simulation Statistics ----------
-host_inst_rate 1501109 # Simulator instruction rate (inst/s)
-host_mem_usage 146480 # Number of bytes of host memory used
-host_seconds 0.33 # Real time elapsed on the host
-host_tick_rate 1499216 # Simulator tick rate (ticks/s)
+host_inst_rate 1431500 # Simulator instruction rate (inst/s)
+host_mem_usage 146556 # Number of bytes of host memory used
+host_seconds 0.35 # Real time elapsed on the host
+host_tick_rate 1429839 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 500000 # Number of instructions simulated
sim_seconds 0.000000 # Number of seconds simulated
All Rights Reserved
-M5 compiled Aug 16 2006 13:05:10
-M5 started Wed Aug 16 14:41:54 2006
+M5 compiled Aug 18 2006 00:06:43
+M5 started Fri Aug 18 00:12:49 2006
M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/test/opt/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-atomic tests/run.py quick/20.eio-short/alpha/eio/simple-atomic
Exiting @ tick 499999 because a thread reached the max instruction count
[system.cpu]
type=TimingSimpleCPU
-children=workload
+children=dcache icache l2cache toL2Bus workload
clock=1
defer_registration=false
function_trace=false
max_insts_any_thread=500000
max_loads_all_threads=0
max_loads_any_thread=0
-mem=system.physmem
+mem=system.cpu.dcache
system=system
workload=system.cpu.workload
+[system.cpu.dcache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+do_copy=false
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=262144
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+
+[system.cpu.icache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+do_copy=false
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=131072
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+
+[system.cpu.l2cache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+do_copy=false
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=2097152
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+
[system.cpu.workload]
type=EioProcess
chkpt=
type=PhysicalMemory
file=
latency=1
+range=0:134217727
[trace]
bufsize=0
[system.physmem]
type=PhysicalMemory
file=
-// range not specified
+range=[0,134217727]
latency=1
[system]
type=Bus
bus_id=0
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
[system.cpu.workload]
type=EioProcess
file=tests/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
max_insts_all_threads=0
max_loads_any_thread=0
max_loads_all_threads=0
-mem=system.physmem
+mem=system.cpu.dcache
system=system
workload=system.cpu.workload
clock=1
function_trace_start=0
// simulate_stalls not specified
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+
+[system.cpu.icache]
+type=BaseCache
+size=131072
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.l2cache]
+type=BaseCache
+size=2097152
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+do_copy=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
[trace]
flags=
start=0
---------- Begin Simulation Statistics ----------
-host_inst_rate 833953 # Simulator instruction rate (inst/s)
-host_mem_usage 146496 # Number of bytes of host memory used
-host_seconds 0.60 # Real time elapsed on the host
-host_tick_rate 1134676 # Simulator tick rate (ticks/s)
+host_inst_rate 619761 # Simulator instruction rate (inst/s)
+host_mem_usage 158236 # Number of bytes of host memory used
+host_seconds 0.81 # Real time elapsed on the host
+host_tick_rate 845354 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 500000 # Number of instructions simulated
sim_seconds 0.000001 # Number of seconds simulated
-sim_ticks 680774 # Number of ticks simulated
+sim_ticks 682354 # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses 124564 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency -2174448991928520960 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 124315 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency -541437798990201749504 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.001999 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 249 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 496 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.001991 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 248 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 56744 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency -6113309131580347 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 56412 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency -2029618631684675072 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.005851 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 332 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 278 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.002450 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 311.061962 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 181308 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency -935400030330269184 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 180727 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency -543467417621886402560 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.003204 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 581 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 774 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.002134 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 387 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 181308 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency -935400030330269184 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 180727 # number of overall hits
+system.cpu.dcache.overall_miss_latency -543467417621886402560 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.003204 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 581 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 774 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.002134 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 387 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.sampled_refs 581 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 347.118131 # Cycle average of tags in use
+system.cpu.dcache.total_refs 180727 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 0 # number of writebacks
+system.cpu.icache.ReadReq_accesses 500000 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency -561967136127090496 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 2 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 499597 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency -226472755859217481728 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000806 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 403 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency 806 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000806 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 403 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 1239.694789 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 500000 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency -561967136127090496 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 2 # average overall mshr miss latency
+system.cpu.icache.demand_hits 499597 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency -226472755859217481728 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000806 # miss rate for demand accesses
+system.cpu.icache.demand_misses 403 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 806 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000806 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 403 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 500000 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency -561967136127090496 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 2 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 499597 # number of overall hits
+system.cpu.icache.overall_miss_latency -226472755859217481728 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000806 # miss rate for overall accesses
+system.cpu.icache.overall_misses 403 # number of overall misses
+system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 806 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000806 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 403 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements 0 # number of replacements
+system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 268.434590 # Cycle average of tags in use
+system.cpu.icache.total_refs 499597 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.l2cache.ReadReq_accesses 984 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 1.605691 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_miss_latency 1580 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 984 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 790 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.802846 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 790 # number of ReadReq MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 984 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 1.605691 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 1 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 1580 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 984 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 790 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.802846 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 790 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 984 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 1.605691 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 1 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 0 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 1580 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 984 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 790 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.802846 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 790 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.sampled_refs 984 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 615.553879 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 0 # number of cpu cycles simulated
system.cpu.num_insts 500000 # Number of instructions executed
All Rights Reserved
-M5 compiled Aug 16 2006 17:47:32
-M5 started Wed Aug 16 18:40:03 2006
+M5 compiled Aug 18 2006 00:06:43
+M5 started Fri Aug 18 00:12:49 2006
M5 executing on zizzer.eecs.umich.edu
-command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/test/opt/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing
-Exiting @ tick 680774 because a thread reached the max instruction count
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing tests/run.py quick/20.eio-short/alpha/eio/simple-timing
+Exiting @ tick 682354 because a thread reached the max instruction count
projects / gem5.git / commitdiff