rmesa->radeon.tcl.elt_dma_bo,
rmesa->radeon.tcl.elt_dma_offset,
RADEON_GEM_DOMAIN_GTT, 0, 0);
- OUT_BATCH(vertex_count/2);
+ OUT_BATCH((vertex_count + 1)/2);
} else {
OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2);
OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810);
OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset);
- OUT_BATCH(vertex_count/2);
+ OUT_BATCH((vertex_count + 1)/2);
radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
rmesa->radeon.tcl.elt_dma_bo,
RADEON_GEM_DOMAIN_GTT, 0, 0);
assert( rmesa->radeon.dma.flush == r200FlushElts );
rmesa->radeon.dma.flush = NULL;
- elt_used = (elt_used + 2) & ~2;
-
nr = elt_used / 2;
radeon_bo_unmap(rmesa->radeon.tcl.elt_dma_bo);
radeonContextPtr radeon = RADEON_CONTEXT( ctx );
int i;
+ if (radeon->dma.flush) {
+ radeon->dma.flush(radeon->glCtx);
+ }
if (radeon->tcl.elt_dma_bo) {
radeon_bo_unref(radeon->tcl.elt_dma_bo);
radeon->tcl.elt_dma_bo = NULL;