Simplify test case script

diff --git a/tests/various/dynamic_part_select.ys b/tests/various/dynamic_part_select.ys
index 24c389068cc10e6b0a15be0432842c6be0423d15..d7fa1417347517cbf773db8e566740d363b577ff 100644 (file)
--- a/tests/various/dynamic_part_select.ys
+++ b/tests/various/dynamic_part_select.ys
@@ -1,13 +1,11 @@
 ### Original testcase ###
 read_verilog ./dynamic_part_select/original.v
-hierarchy -top original; proc; opt;
-prep -flatten -top original
+proc
 rename -top gold
 design -stash gold
 
 read_verilog ./dynamic_part_select/original_gate.v
-hierarchy -top original_gate; proc; opt;
-prep -flatten -top original_gate
+proc
 rename -top gate
 design -stash gate
 
@@ -15,19 +13,17 @@ design -copy-from gold -as gold gold
 design -copy-from gate -as gate gate
 
 miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
-hierarchy -top equiv
 sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv
 
 ### Multiple blocking assingments ###
+design -reset
 read_verilog ./dynamic_part_select/multiple_blocking.v
-hierarchy -top multiple_blocking; proc; opt;
-prep -flatten -top multiple_blocking
+proc
 rename -top gold
 design -stash gold
  
 read_verilog ./dynamic_part_select/multiple_blocking_gate.v
-hierarchy -top multiple_blocking_gate; proc; opt;
-prep -flatten -top multiple_blocking_gate
+proc
 rename -top gate
 design -stash gate
  
@@ -35,19 +31,17 @@ design -copy-from gold -as gold gold
 design -copy-from gate -as gate gate
 
 miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
-hierarchy -top equiv
 sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv
  
 ### Non-blocking to the same output register ###
+design -reset
 read_verilog ./dynamic_part_select/nonblocking.v
-hierarchy -top nonblocking; proc; opt;
-prep -flatten -top nonblocking
+proc
 rename -top gold
 design -stash gold
 
 read_verilog ./dynamic_part_select/nonblocking_gate.v
-hierarchy -top nonblocking_gate; proc; opt;
-prep -flatten -top nonblocking_gate
+proc
 rename -top gate
 design -stash gate
  
@@ -55,19 +49,17 @@ design -copy-from gold -as gold gold
 design -copy-from gate -as gate gate
 
 miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
-hierarchy -top equiv
 sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv
  
 ### For-loop select, one dynamic input
+design -reset
 read_verilog ./dynamic_part_select/forloop_select.v
-hierarchy -top forloop_select; proc; opt;
-prep -flatten -top forloop_select
+proc
 rename -top gold
 design -stash gold
 
 read_verilog ./dynamic_part_select/forloop_select_gate.v
-hierarchy -top forloop_select_gate; proc; opt;
-prep -flatten -top forloop_select_gate
+proc
 rename -top gate
 design -stash gate
  
@@ -75,19 +67,17 @@ design -copy-from gold -as gold gold
 design -copy-from gate -as gate gate
 
 miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
-hierarchy -top equiv
 sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv
  
 #### Double loop (part-select, reset) ### 
+design -reset
 read_verilog ./dynamic_part_select/reset_test.v
-hierarchy -top reset_test; proc; opt;
-prep -flatten -top reset_test
+proc
 rename -top gold
 design -stash gold
 
 read_verilog ./dynamic_part_select/reset_test_gate.v
-hierarchy -top reset_test_gate; proc; opt;
-prep -flatten -top reset_test_gate
+proc
 rename -top gate
 design -stash gate
 
@@ -95,19 +85,17 @@ design -copy-from gold -as gold gold
 design -copy-from gate -as gate gate
  
 miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
-hierarchy -top equiv
 sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv
  
 ### Reversed part-select case ###
+design -reset
 read_verilog ./dynamic_part_select/reversed.v
-hierarchy -top reversed; proc; opt;
-prep -flatten -top reversed
+proc
 rename -top gold
 design -stash gold
 
 read_verilog ./dynamic_part_select/reversed_gate.v
-hierarchy -top reversed_gate; proc; opt;
-prep -flatten -top reversed_gate
+proc
 rename -top gate
 design -stash gate
 
@@ -115,5 +103,4 @@ design -copy-from gold -as gold gold
 design -copy-from gate -as gate gate
  
 miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
-hierarchy -top equiv
 sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv