i965/hsw: Change L3 MOCS of 3DSTATE_VERTEX_BUFFERS

Change from "not cacheable" to "cacheable" in L3.
Do so for the draw upload path and blorp.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 2952027ebd736f2004cd606d0213ee9cae9dd42b..897e7331338fe09258d0e3ff8f826e2ef0c46c7e 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -658,6 +658,9 @@ static void brw_emit_vertices(struct brw_context *brw)
         if (brw->gen >= 7)
            dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE;
 
+        if (brw->is_haswell)
+           dw0 |= GEN7_MOCS_L3 << 16;
+
         OUT_BATCH(dw0 | (buffer->stride << BRW_VB0_PITCH_SHIFT));
         OUT_RELOC(buffer->bo, I915_GEM_DOMAIN_VERTEX, 0, buffer->offset);
         if (brw->gen >= 5) {

diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 8056bf557a1a0ea4505edd8a94662b6614fd8042..a4a90817a8c2cb8e5a2fc8119a234863d92acd5f 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -163,6 +163,9 @@ gen6_blorp_emit_vertices(struct brw_context *brw,
       if (brw->gen >= 7)
          dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE;
 
+      if (brw->is_haswell)
+         dw0 |= GEN7_MOCS_L3 << 16;
+
       BEGIN_BATCH(batch_length);
       OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (batch_length - 2));
       OUT_BATCH(dw0);