}
struct ir3_shader *
-ir3_shader_from_nir(struct ir3_compiler *compiler, nir_shader *nir)
+ir3_shader_from_nir(struct ir3_compiler *compiler, nir_shader *nir,
+ struct ir3_stream_output_info *stream_output)
{
struct ir3_shader *shader = CALLOC_STRUCT(ir3_shader);
shader->compiler = compiler;
shader->id = p_atomic_inc_return(&shader->compiler->shader_count);
shader->type = nir->info.stage;
+ if (stream_output)
+ memcpy(&shader->stream_output, stream_output, sizeof(shader->stream_output));
NIR_PASS_V(nir, nir_lower_io, nir_var_all, ir3_glsl_type_size,
(nir_lower_io_options)0);
void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id);
struct ir3_shader_variant * ir3_shader_get_variant(struct ir3_shader *shader,
struct ir3_shader_key *key, bool binning_pass, bool *created);
-struct ir3_shader * ir3_shader_from_nir(struct ir3_compiler *compiler, nir_shader *nir);
+struct ir3_shader * ir3_shader_from_nir(struct ir3_compiler *compiler, nir_shader *nir,
+ struct ir3_stream_output_info *stream_output);
void ir3_shader_destroy(struct ir3_shader *shader);
void ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin, FILE *out);
uint64_t ir3_shader_outputs(const struct ir3_shader *so);
nir = tgsi_to_nir(cso->tokens, screen);
}
- struct ir3_shader *shader = ir3_shader_from_nir(compiler, nir);
+ struct ir3_stream_output_info stream_output;
+ copy_stream_out(&stream_output, &cso->stream_output);
- copy_stream_out(&shader->stream_output, &cso->stream_output);
+ struct ir3_shader *shader = ir3_shader_from_nir(compiler, nir, &stream_output);
if (fd_mesa_debug & FD_DBG_SHADERDB) {
/* if shader-db run, create a standard variant immediately
nir = tgsi_to_nir(cso->prog, screen);
}
- struct ir3_shader *shader = ir3_shader_from_nir(compiler, nir);
+ struct ir3_shader *shader = ir3_shader_from_nir(compiler, nir, NULL);
if (fd_mesa_debug & FD_DBG_SHADERDB) {
/* if shader-db run, create a standard variant immediately