split muxes synth per type

diff --git a/tests/xilinx/mux.v b/tests/xilinx/mux.v
index 0814b733e5b889ab6a6cac6154ea6f1717b054ca..27bc0bf0b29484caa56e248ac706355bedee32b3 100644 (file)
--- a/tests/xilinx/mux.v
+++ b/tests/xilinx/mux.v
@@ -63,38 +63,3 @@ module mux16 (D, S, Y);
 assign Y = D[S];
 
 endmodule
-
-
-module top (
-input [3:0] S,
-input [15:0] D,
-output M2,M4,M8,M16
-);
-
-mux2 u_mux2 (
-        .S (S[0]),
-        .A (D[0]),
-        .B (D[1]),
-        .Y (M2)
-    );
-
-
-mux4 u_mux4 (
-        .S (S[1:0]),
-        .D (D[3:0]),
-        .Y (M4)
-    );
-
-mux8 u_mux8 (
-        .S (S[2:0]),
-        .D (D[7:0]),
-        .Y (M8)
-    );
-
-mux16 u_mux16 (
-        .S (S[3:0]),
-        .D (D[15:0]),
-        .Y (M16)
-    );
-
-endmodule

diff --git a/tests/xilinx/mux.ys b/tests/xilinx/mux.ys
index 6ecee58f588bf7828f41b41d9948fb54acccfee6..4cdb12e47f4dd6e260d21d08ec71ed288cae634c 100644 (file)
--- a/tests/xilinx/mux.ys
+++ b/tests/xilinx/mux.ys
@@ -1,10 +1,45 @@
 read_verilog mux.v
+design -save read
+
+proc
+hierarchy -top mux2
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux2 # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT3
+
+select -assert-none t:LUT3 %% t:* %D
+
+
+design -load read
 proc
-flatten
+hierarchy -top mux4
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd mux4 # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT6
+
+select -assert-none t:LUT6 %% t:* %D
+
+
+design -load read
+proc
+hierarchy -top mux8
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux8 # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT3
+select -assert-count 2 t:LUT6
 
-select -assert-count 2  t:LUT3
-select -assert-count 5  t:LUT6
 select -assert-none t:LUT3 t:LUT6 %% t:* %D
+
+
+design -load read
+proc
+hierarchy -top mux16
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux16 # Constrain all select calls below inside the top module
+select -assert-count 5 t:LUT6
+
+select -assert-none t:LUT6 %% t:* %D