fhdl/verilog: properly connect instance inouts

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index 3b6655e781fedc45faa47007cd33cbf5b99daeb9..e68071aece9b807c0bfde033f49c214d74ba34e4 100644 (file)
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -198,7 +198,7 @@ def _printinstances(f, ns, clk, rst):
                r += ns.get_name(x) 
                if x.parameters: r += " "
                r += "(\n"
-               ports = list(x.ins.items()) + list(x.outs.items())
+               ports = list(x.ins.items()) + list(x.outs.items()) + list(x.inouts.items())
                if x.clkport:
                        ports.append((x.clkport, clk))
                if x.rstport: