[ARM] Fix PR target/59833

For Aurelien Jarno <aurelien@aurel32.net>

On ARM soft-float, the float to double conversion doesn't convert a sNaN
to qNaN as the IEEE Std 754 standard mandates:

"Under default exception handling, any operation signaling an invalid
operation exception and for which a floating-point result is to be
delivered shall deliver a quiet NaN."

Given the soft float ARM code ignores exceptions and always provides a
result, a float to double conversion of a signaling NaN should return a
quiet NaN. Fix this in extendsfdf2.

gcc/ChangeLog:

	PR target/59833
	* config/arm/ieee754-df.S (extendsfdf2): Convert sNaN to qNaN.

gcc/testsuite/ChangeLog:

	* gcc.dg/pr59833.c: New testcase.

From-SVN: r238584

diff --git a/gcc/testsuite/gcc.dg/pr59833.c b/gcc/testsuite/gcc.dg/pr59833.c
new file mode 100644 (file)
index 0000000..e0e4ed5
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr59833.c
@@ -0,0 +1,18 @@
+/* { dg-do run { target { *-*-linux* *-*-gnu* } } } */
+/* { dg-options "-O0 -lm" } */
+/* { dg-require-effective-target issignaling } */
+
+#define _GNU_SOURCE
+#include <math.h>
+
+int main (void)
+{
+  float sNaN = __builtin_nansf ("");
+  double x = (double) sNaN;
+  if (issignaling(x))
+  {
+    __builtin_abort();
+  }
+
+  return 0;
+}

diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index f2d7114cb498a48afa066279a43f758fc7f8c3a4..f3e9104f8964d1d7e729a967389bbed8aaada88e 100644 (file)
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,8 @@
+2016-07-21  Aurelien Jarno <aurelien@aurel32.net>
+
+       PR target/59833
+       * config/arm/ieee754-df.S (extendsfdf2): Convert sNaN to qNaN.
+
 2016-07-19  Nick Clifton  <nickc@redhat.com>
 
        * config.host (m32r): Add m32r/t-m32r to tmake_file.

diff --git a/libgcc/config/arm/ieee754-df.S b/libgcc/config/arm/ieee754-df.S
index a2aac702e6c990e62cc94a68491eaa2292b478fb..1ecaa9dac2053267d39b8b5948b8a303afca760d 100644 (file)
--- a/libgcc/config/arm/ieee754-df.S
+++ b/libgcc/config/arm/ieee754-df.S
@@ -507,11 +507,15 @@ ARM_FUNC_ALIAS aeabi_f2d extendsfdf2
        eorne   xh, xh, #0x38000000     @ fixup exponent otherwise.
        RETc(ne)                        @ and return it.
 
-       teq     r2, #0                  @ if actually 0
-       do_it   ne, e
-       teqne   r3, #0xff000000         @ or INF or NAN
+       bics    r2, r2, #0xff000000     @ isolate mantissa
+       do_it   eq                      @ if 0, that is ZERO or INF,
        RETc(eq)                        @ we are done already.
 
+       teq     r3, #0xff000000         @ check for NAN
+       do_it   eq, t
+       orreq   xh, xh, #0x00080000     @ change to quiet NAN
+       RETc(eq)                        @ and return it.
+
        @ value was denormalized.  We can normalize it now.
        do_push {r4, r5, lr}
        .cfi_adjust_cfa_offset 12   @ CFA is now sp + previousOffset + 12