s390.md ("*fmadddf", [...]): New insns.

	* config/s390/s390.md ("*fmadddf", "*fmsubdf",
	"*fmaddsf", "*fmsubsf"): New insns.

From-SVN: r70811

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 1b7d9708fa6be2706fa27e674062283f6a441d6c..481a92659b6d8d79775b5d2ab2b4c1da0d702154 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2003-08-26  Andreas Krebbel <krebbel1@de.ibm.com>
+
+       * config/s390/s390.md ("*fmadddf", "*fmsubdf", 
+       "*fmaddsf", "*fmsubsf"): New insns.
+
 2003-08-26  Roger Sayle  <roger@eyesopen.com>
 
        * fold-const.c (fold <MULT_EXPR>): Optimize (C1/X)*C2 into

diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index a190bad72b8f3b5483eb968d63389abda600a609..d9e65439af069cf1be85e55b0471322ad75da2e1 100644 (file)
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -4047,6 +4047,30 @@
   [(set_attr "op_type"  "RR,RX")
    (set_attr "type"    "fmuld")])
 
+(define_insn "*fmadddf"
+  [(set (match_operand:DF 0 "register_operand" "=f,f")
+       (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "%f,f")
+                         (match_operand:DF 2 "nonimmediate_operand"  "f,R"))
+                (match_operand:DF 3 "register_operand" "0,0")))]
+  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && flag_unsafe_math_optimizations"
+  "@
+   madbr\t%0,%1,%2
+   madb\t%0,%1,%2"
+  [(set_attr "op_type"  "RRE,RXE")
+   (set_attr "type" "fmuld")])
+
+(define_insn "*fmsubdf"
+  [(set (match_operand:DF 0 "register_operand" "=f,f")
+       (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f,f")
+                          (match_operand:DF 2 "nonimmediate_operand"  "f,R"))
+                (match_operand:DF 3 "register_operand" "0,0")))]
+  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && flag_unsafe_math_optimizations"
+  "@
+   msdbr\t%0,%1,%2
+   msdb\t%0,%1,%2"
+  [(set_attr "op_type"  "RRE,RXE")
+   (set_attr "type" "fmuld")])
+
 ;
 ; mulsf3 instruction pattern(s).
 ;
@@ -4084,6 +4108,29 @@
   [(set_attr "op_type"  "RR,RX")
    (set_attr "type"     "fmuls")])
 
+(define_insn "*fmaddsf"
+  [(set (match_operand:SF 0 "register_operand" "=f,f")
+       (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%f,f")
+                         (match_operand:SF 2 "nonimmediate_operand"  "f,R"))
+                (match_operand:SF 3 "register_operand" "0,0")))]
+  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && flag_unsafe_math_optimizations"
+  "@
+   maebr\t%0,%1,%2
+   maeb\t%0,%1,%2"
+  [(set_attr "op_type"  "RRE,RXE")
+   (set_attr "type" "fmuls")])
+
+(define_insn "*fmsubsf"
+  [(set (match_operand:SF 0 "register_operand" "=f,f")
+       (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f,f")
+                          (match_operand:SF 2 "nonimmediate_operand"  "f,R"))
+                 (match_operand:SF 3 "register_operand" "0,0")))]
+  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && flag_unsafe_math_optimizations"
+  "@
+   msebr\t%0,%1,%2
+   mseb\t%0,%1,%2"
+  [(set_attr "op_type"  "RRE,RXE")
+   (set_attr "type" "fmuls")])
 
 ;;
 ;;- Divide and modulo instructions.