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diff --git a/nlnet_2022_ongoing/discussion.mdwn b/nlnet_2022_ongoing/discussion.mdwn
index 7e567129f693a57850178fb44c0c63d930216a4d..41dbc0b14ff65ae459bb9e1795a592e061bceeb3 100644 (file)
--- a/nlnet_2022_ongoing/discussion.mdwn
+++ b/nlnet_2022_ongoing/discussion.mdwn
@@ -44,5 +44,21 @@ necessary infrastructure (Dynamic SIMD, IEEE754 ALUs) first.
 Answering on the ASIC first: it is a little early to tell.  Coriolis2 needs Timing
 based Routing completed in order to tackle lower geometries (even 90nm),
 https://libre-soc.org/nlnet_2021_lip6_vlsi/ 2021-08-049 - and sky130
-is far too small an allocation (12 mm^2 when we need around 100)
+is far too small an allocation (12 mm^2 when we need around 100).
+Given the amount of time it took (I have to admit it was a major time-sink for me)
+I am happy to wait until coriolis2 is more feature-ready.  Powerful FPGAs
+get us a long way.
+
+The concrete outcomes:
+
+* A greatly increased strategic capacity of nmigen HDL: full Object-Orientated
+  Abstraction of its core Language Features.  Opportunities then open up
+  to perform strict type checking, length checking, other types of Arithmetic
+  (Complex numbers, Galois Field) and other "filters" as
+  3rd party extensions, of which the Dynamic SIMD Partitioning created under
+  2019-02-012 would be the first big showcase.
+* A modern well-documented IEEE754 Floating-Point Library, with Formal Correctess
+  Proofs using modern FOSSHW tools is a big deal in its own right. The only
+  other Libre Formal Proof is for an older version of IEEE754, we will
+  target 2008 and 2019 semantics.