mem: Rename the ruby Prefetcher class RubyPrefetcher.

A new Prefetcher namespace was added which holds the gem5 prefetchers
and means they don't all need a "Prefetcher" in their name. Unfortunately
that means that there is now both a Prefetcher namespace and a
Prefetcher class which conflict with each other.

This change tries to resolve the conflict with as little disruption as
possible by simply renaming the c++ ruby Pretcher class RubyPrefetcher,
leaving the python name alone so that configs aren't affected.

Issue-on: https://gem5.atlassian.net/browse/GEM5-447

Change-Id: I7afdf5dbc57dbf46d82552113c52f3a9207870f2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27949
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/mem/ruby/structures/Prefetcher.cc b/src/mem/ruby/structures/Prefetcher.cc
index a8b2d855710dab4c36c02815c2446062bde2d21f..06021159c9dbf1ef5122ecb504cb4705ce08a3a8 100644 (file)
--- a/src/mem/ruby/structures/Prefetcher.cc
+++ b/src/mem/ruby/structures/Prefetcher.cc
@@ -45,13 +45,13 @@
 #include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
 #include "mem/ruby/system/RubySystem.hh"
 
-Prefetcher*
+RubyPrefetcher*
 PrefetcherParams::create()
 {
-    return new Prefetcher(this);
+    return new RubyPrefetcher(this);
 }
 
-Prefetcher::Prefetcher(const Params *p)
+RubyPrefetcher::RubyPrefetcher(const Params *p)
     : SimObject(p), m_num_streams(p->num_streams),
     m_array(p->num_streams), m_train_misses(p->train_misses),
     m_num_startup_pfs(p->num_startup_pfs), m_num_unit_filters(p->unit_filter),
@@ -89,7 +89,7 @@ Prefetcher::Prefetcher(const Params *p)
     }
 }
 
-Prefetcher::~Prefetcher()
+RubyPrefetcher::~RubyPrefetcher()
 {
     delete m_unit_filter_hit;
     delete m_negative_filter_hit;
@@ -98,7 +98,7 @@ Prefetcher::~Prefetcher()
 }
 
 void
-Prefetcher::regStats()
+RubyPrefetcher::regStats()
 {
     SimObject::regStats();
 
@@ -139,7 +139,7 @@ Prefetcher::regStats()
 }
 
 void
-Prefetcher::observeMiss(Addr address, const RubyRequestType& type)
+RubyPrefetcher::observeMiss(Addr address, const RubyRequestType& type)
 {
     DPRINTF(RubyPrefetcher, "Observed miss for %#x\n", address);
     Addr line_addr = makeLineAddress(address);
@@ -207,7 +207,7 @@ Prefetcher::observeMiss(Addr address, const RubyRequestType& type)
 }
 
 void
-Prefetcher::observePfMiss(Addr address)
+RubyPrefetcher::observePfMiss(Addr address)
 {
     numPartialHits++;
     DPRINTF(RubyPrefetcher, "Observed partial hit for %#x\n", address);
@@ -215,7 +215,7 @@ Prefetcher::observePfMiss(Addr address)
 }
 
 void
-Prefetcher::observePfHit(Addr address)
+RubyPrefetcher::observePfHit(Addr address)
 {
     numHits++;
     DPRINTF(RubyPrefetcher, "Observed hit for %#x\n", address);
@@ -223,7 +223,7 @@ Prefetcher::observePfHit(Addr address)
 }
 
 void
-Prefetcher::issueNextPrefetch(Addr address, PrefetchEntry *stream)
+RubyPrefetcher::issueNextPrefetch(Addr address, PrefetchEntry *stream)
 {
     // get our corresponding stream fetcher
     if (stream == NULL) {
@@ -262,7 +262,7 @@ Prefetcher::issueNextPrefetch(Addr address, PrefetchEntry *stream)
 }
 
 uint32_t
-Prefetcher::getLRUindex(void)
+RubyPrefetcher::getLRUindex(void)
 {
     uint32_t lru_index = 0;
     Cycles lru_access = m_array[lru_index].m_use_time;
@@ -281,7 +281,7 @@ Prefetcher::getLRUindex(void)
 }
 
 void
-Prefetcher::clearNonunitEntry(uint32_t index)
+RubyPrefetcher::clearNonunitEntry(uint32_t index)
 {
     m_nonunit_filter[index] = 0;
     m_nonunit_stride[index] = 0;
@@ -289,7 +289,7 @@ Prefetcher::clearNonunitEntry(uint32_t index)
 }
 
 void
-Prefetcher::initializeStream(Addr address, int stride,
+RubyPrefetcher::initializeStream(Addr address, int stride,
      uint32_t index, const RubyRequestType& type)
 {
     numAllocatedStreams++;
@@ -330,7 +330,7 @@ Prefetcher::initializeStream(Addr address, int stride,
 }
 
 PrefetchEntry *
-Prefetcher::getPrefetchEntry(Addr address, uint32_t &index)
+RubyPrefetcher::getPrefetchEntry(Addr address, uint32_t &index)
 {
     // search all streams for a match
     for (int i = 0; i < m_num_streams; i++) {
@@ -348,7 +348,7 @@ Prefetcher::getPrefetchEntry(Addr address, uint32_t &index)
 }
 
 bool
-Prefetcher::accessUnitFilter(std::vector<Addr>& filter_table,
+RubyPrefetcher::accessUnitFilter(std::vector<Addr>& filter_table,
     uint32_t *filter_hit, uint32_t &index, Addr address,
     int stride, bool &alloc)
 {
@@ -381,7 +381,7 @@ Prefetcher::accessUnitFilter(std::vector<Addr>& filter_table,
 }
 
 bool
-Prefetcher::accessNonunitFilter(Addr address, int *stride,
+RubyPrefetcher::accessNonunitFilter(Addr address, int *stride,
     bool &alloc)
 {
     //reset the alloc flag
@@ -444,7 +444,7 @@ Prefetcher::accessNonunitFilter(Addr address, int *stride,
 }
 
 void
-Prefetcher::print(std::ostream& out) const
+RubyPrefetcher::print(std::ostream& out) const
 {
     out << name() << " Prefetcher State\n";
     // print out unit filter
@@ -477,7 +477,7 @@ Prefetcher::print(std::ostream& out) const
 }
 
 Addr
-Prefetcher::pageAddress(Addr addr) const
+RubyPrefetcher::pageAddress(Addr addr) const
 {
     return mbits<Addr>(addr, 63, m_page_shift);
 }

diff --git a/src/mem/ruby/structures/Prefetcher.hh b/src/mem/ruby/structures/Prefetcher.hh
index 89c0186a76ada62a4e460dee6b73e29ba0b59ba9..4d2513f78d7f1d8227dd950b6c29f7e76864ecd9 100644 (file)
--- a/src/mem/ruby/structures/Prefetcher.hh
+++ b/src/mem/ruby/structures/Prefetcher.hh
@@ -90,12 +90,12 @@ class PrefetchEntry
         std::bitset<MAX_PF_INFLIGHT> requestCompleted;
 };
 
-class Prefetcher : public SimObject
+class RubyPrefetcher : public SimObject
 {
     public:
         typedef PrefetcherParams Params;
-        Prefetcher(const Params *p);
-        ~Prefetcher();
+        RubyPrefetcher(const Params *p);
+        ~RubyPrefetcher();
 
         void issueNextPrefetch(Addr address, PrefetchEntry *stream);
         /**

diff --git a/src/mem/ruby/structures/RubyPrefetcher.py b/src/mem/ruby/structures/RubyPrefetcher.py
index 9d2803b34567c0b3fd759e154bac370160cf4156..d762ba5308bbccff21900fd97a9f651e036f6661 100644 (file)
--- a/src/mem/ruby/structures/RubyPrefetcher.py
+++ b/src/mem/ruby/structures/RubyPrefetcher.py
@@ -44,7 +44,7 @@ from m5.objects.System import System
 
 class Prefetcher(SimObject):
     type = 'Prefetcher'
-    cxx_class = 'Prefetcher'
+    cxx_class = 'RubyPrefetcher'
     cxx_header = "mem/ruby/structures/Prefetcher.hh"
 
     num_streams = Param.UInt32(4,