}
+/* Translate the following TGSI CEIL instruction.
+ * CEIL DST, SRC
+ * To the following SVGA3D instruction sequence.
+ * FRC TMP, -SRC
+ * ADD DST, SRC, TMP
+ */
+static boolean emit_ceil(struct svga_shader_emitter *emit,
+ const struct tgsi_full_instruction *insn)
+{
+ SVGA3dShaderDestToken dst = translate_dst_register(emit, insn, 0);
+ const struct src_register src0 = translate_src_register(emit, &insn->Src[0]);
+ SVGA3dShaderDestToken temp = get_temp(emit);
+
+ /* FRC TMP, -SRC */
+ if (!submit_op1(emit, inst_token(SVGA3DOP_FRC), temp, negate(src0)))
+ return FALSE;
+
+ /* ADD DST, SRC, TMP */
+ if (!submit_op2(emit, inst_token(SVGA3DOP_ADD), dst, src0, src(temp)))
+ return FALSE;
+
+ return TRUE;
+}
+
+
/* Translate the following TGSI CMP instruction.
* CMP DST, SRC0, SRC1, SRC2
* To the following SVGA3D instruction sequence.
case TGSI_OPCODE_TRUNC: /* should be TRUNC, not FLR */
return emit_floor( emit, insn );
+ case TGSI_OPCODE_CEIL:
+ return emit_ceil( emit, insn );
+
case TGSI_OPCODE_CMP:
return emit_cmp( emit, insn );