Avoid parameter values with size 0 ($mem cells)

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 6de5846f93ae2fb23d590cf7d68455717681ecc0..2dff53b7bbc469ccb6ccea190f051c8c66b75388 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -918,11 +918,11 @@ namespace {
                                param("\\SIZE");
                                param("\\OFFSET");
                                param("\\INIT");
-                               param_bits("\\RD_CLK_ENABLE", param("\\RD_PORTS"));
-                               param_bits("\\RD_CLK_POLARITY", param("\\RD_PORTS"));
-                               param_bits("\\RD_TRANSPARENT", param("\\RD_PORTS"));
-                               param_bits("\\WR_CLK_ENABLE", param("\\WR_PORTS"));
-                               param_bits("\\WR_CLK_POLARITY", param("\\WR_PORTS"));
+                               param_bits("\\RD_CLK_ENABLE", std::max(1, param("\\RD_PORTS")));
+                               param_bits("\\RD_CLK_POLARITY", std::max(1, param("\\RD_PORTS")));
+                               param_bits("\\RD_TRANSPARENT", std::max(1, param("\\RD_PORTS")));
+                               param_bits("\\WR_CLK_ENABLE", std::max(1, param("\\WR_PORTS")));
+                               param_bits("\\WR_CLK_POLARITY", std::max(1, param("\\WR_PORTS")));
                                port("\\RD_CLK", param("\\RD_PORTS"));
                                port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
                                port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));

diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
index 96d0ada03fa3b050506de269dd1435364c9252f8..7e088a1b093296a78b8794ed055ef23fd09a5ba0 100644 (file)
--- a/passes/memory/memory_collect.cc
+++ b/passes/memory/memory_collect.cc
@@ -178,8 +178,8 @@ void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
        log_assert(sig_wr_en.size() == wr_ports * memory->width);
 
        mem->parameters["\\WR_PORTS"] = RTLIL::Const(wr_ports);
-       mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : RTLIL::Const(0, 0);
-       mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.as_const() : RTLIL::Const(0, 0);
+       mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : RTLIL::Const(0, 1);
+       mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.as_const() : RTLIL::Const(0, 1);
 
        mem->setPort("\\WR_CLK", sig_wr_clk);
        mem->setPort("\\WR_ADDR", sig_wr_addr);
@@ -193,9 +193,9 @@ void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
        log_assert(sig_rd_data.size() == rd_ports * memory->width);
 
        mem->parameters["\\RD_PORTS"] = RTLIL::Const(rd_ports);
-       mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.as_const() : RTLIL::Const(0, 0);
-       mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.as_const() : RTLIL::Const(0, 0);
-       mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.as_const() : RTLIL::Const(0, 0);
+       mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.as_const() : RTLIL::Const(0, 1);
+       mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.as_const() : RTLIL::Const(0, 1);
+       mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.as_const() : RTLIL::Const(0, 1);
 
        mem->setPort("\\RD_CLK", sig_rd_clk);
        mem->setPort("\\RD_ADDR", sig_rd_addr);

diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc
index 41c4a7b124cee77a08928fa497e0aeb457bc4bb4..bc94e1e25ad84b96fc2f7a8e6bbba27afd3b9052 100644 (file)
--- a/passes/memory/memory_map.cc
+++ b/passes/memory/memory_map.cc
@@ -81,6 +81,9 @@ struct MemoryMapWorker
                std::set<int> static_ports;
                std::map<int, RTLIL::SigSpec> static_cells_map;
 
+               int wr_ports = cell->parameters["\\WR_PORTS"].as_int();
+               int rd_ports = cell->parameters["\\RD_PORTS"].as_int();
+
                int mem_size = cell->parameters["\\SIZE"].as_int();
                int mem_width = cell->parameters["\\WIDTH"].as_int();
                int mem_offset = cell->parameters["\\OFFSET"].as_int();
@@ -90,7 +93,7 @@ struct MemoryMapWorker
                init_data.extend_u0(mem_size*mem_width, true);
 
                // delete unused memory cell
-               if (cell->parameters["\\RD_PORTS"].as_int() == 0 && cell->parameters["\\WR_PORTS"].as_int() == 0) {
+               if (wr_ports == 0 && rd_ports == 0) {
                        module->remove(cell);
                        return;
                }
@@ -99,6 +102,8 @@ struct MemoryMapWorker
                RTLIL::SigSpec clocks = cell->getPort("\\WR_CLK");
                RTLIL::Const clocks_pol = cell->parameters["\\WR_CLK_POLARITY"];
                RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"];
+               clocks_pol.bits.resize(wr_ports);
+               clocks_en.bits.resize(wr_ports);
                RTLIL::SigSpec refclock;
                RTLIL::State refclock_pol = RTLIL::State::Sx;
                for (int i = 0; i < clocks.size(); i++) {