(no commit message)

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index ee1148c2c1b763e02514b406ef27d0515ce07314..90e8589525806d61993cdb64578c2c129cfb6139 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -378,8 +378,8 @@ Integer and Floating-point Scalar register files were dropped approximately
 a decade ago after the Packed SIMD variants were considered to be
 duplicates.  With it being completely inappropriate to attempt to Vectorise
 a Packed SIMD ISA designed 20 years ago with no Predication of any kind,
-the Scalar ISA, a much better all-round candidate for Vectorisation is
-left anaemic.
+the Scalar ISA, a much better all-round candidate for Vectorisation 
+(the Scalar parts of Power ISA) is left anaemic.
 
 A particular key instruction that is missing is `MV.X` which is
 illustrated as `GPR(dest) = GPR(GPR(src))`. This horrendously