arch: Explicitly specify the endianness in the generic mem helpers.

This avoids using the accessors which automatically assume an
endianness, requiring the memory system to know what the guest ISA is.

Change-Id: I863fa4116f00e77b801a2f8ea2fbe34e7f55fd5f
Reviewed-on: https://gem5-review.googlesource.com/c/13461
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

diff --git a/src/arch/generic/memhelpers.hh b/src/arch/generic/memhelpers.hh
index 6fe1707a0d36f5886d2b7a3dc67391ecf7f68f8a..7fd4f70de8a5a60052132285ff7f025aa41b65c1 100644 (file)
--- a/src/arch/generic/memhelpers.hh
+++ b/src/arch/generic/memhelpers.hh
@@ -66,7 +66,7 @@ template <class MemT>
 void
 getMem(PacketPtr pkt, MemT &mem, Trace::InstRecord *traceData)
 {
-    mem = pkt->get<MemT>();
+    mem = pkt->get<MemT>(TheISA::GuestByteOrder);
     if (traceData)
         traceData->setData(mem);
 }

diff --git a/src/arch/generic/mmapped_ipr.cc b/src/arch/generic/mmapped_ipr.cc
index c908eff01064827e28551c194eac5ee70e477b26..14e2bafbd4ec677ec1f0fcd9c4b6bd63ec2a3d4f 100644 (file)
--- a/src/arch/generic/mmapped_ipr.cc
+++ b/src/arch/generic/mmapped_ipr.cc
@@ -47,7 +47,7 @@ handlePseudoInst(ThreadContext *xc, Packet *pkt)
     assert((offset >> 16) == 0);
     ret = PseudoInst::pseudoInst(xc, func, subfunc);
     if (pkt->isRead())
-        pkt->set(ret);
+        pkt->set(ret, TheISA::GuestByteOrder);
 }
 
 Cycles