add preamble on reg field encoding

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index 05059e48bff42b1ded2d43ccc27ae020e92451f6..d74004cb7a70c8d44ebd4b217c67d93c9f53287f 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -562,6 +562,14 @@ class SVP64Asm:
             # XXX also TODO: the LD/ST modes which are different
             # https://libre-soc.org/openpower/sv/ldst/
 
+            # rright.  SVP64 register numbering is from 0 to 127
+            # for GPRs, FPRs *and* CR Fields, where for v3.0 the GPRs and RPFs
+            # are 0-31 and CR Fields are only 0-7.  the SVP64 RM "Extra"
+            # area is used to extend the numbering from the 32-bit
+            # instruction, and also to record whether the register
+            # is scalar or vector. on a per-operand basis.  this
+            # results in a slightly finnicky encoding: here we go...
+
             # encode SV-GPR and SV-FPR field into extra, v3.0field
             if rtype in ['GPR', 'FPR']:
                 sv_extra, field = get_extra_gpr(etype, regmode, field)