ctx->num_transfers = ctx->num_draws = ctx->num_compute = 0;
virgl_transfer_queue_clear(&ctx->queue, ctx->cbuf);
- rs->vws->submit_cmd(rs->vws, ctx->cbuf, ctx->cbuf->in_fence_fd,
+ rs->vws->submit_cmd(rs->vws, ctx->cbuf,
ctx->cbuf->needs_out_fence_fd ? &out_fence_fd : NULL);
if (fence)
virgl_flush_eq(vctx, vctx, fence);
- if (vctx->cbuf->in_fence_fd != -1) {
- close(vctx->cbuf->in_fence_fd);
- vctx->cbuf->in_fence_fd = -1;
- }
vctx->cbuf->needs_out_fence_fd = false;
}
struct virgl_cmd_buf {
unsigned cdw;
uint32_t *buf;
- int in_fence_fd;
bool needs_out_fence_fd;
};
void (*emit_res)(struct virgl_winsys *vws, struct virgl_cmd_buf *buf, struct virgl_hw_res *res, boolean write_buffer);
int (*submit_cmd)(struct virgl_winsys *vws, struct virgl_cmd_buf *buf,
- int32_t in_fence_fd, int32_t *out_fence_fd);
+ int32_t *out_fence_fd);
boolean (*res_is_referenced)(struct virgl_winsys *vws,
struct virgl_cmd_buf *buf,
return NULL;
}
+ cbuf->in_fence_fd = -1;
cbuf->base.buf = cbuf->buf;
- cbuf->base.in_fence_fd = -1;
return &cbuf->base;
}
static int virgl_drm_winsys_submit_cmd(struct virgl_winsys *qws,
struct virgl_cmd_buf *_cbuf,
- int in_fence_fd, int *out_fence_fd)
+ int *out_fence_fd)
{
struct virgl_drm_winsys *qdws = virgl_drm_winsys(qws);
struct virgl_drm_cmd_buf *cbuf = virgl_drm_cmd_buf(_cbuf);
eb.size = cbuf->base.cdw * 4;
eb.num_bo_handles = cbuf->cres;
eb.bo_handles = (unsigned long)(void *)cbuf->res_hlist;
+
eb.fence_fd = -1;
+ if (qws->supports_fences) {
+ if (cbuf->in_fence_fd >= 0) {
+ eb.flags |= VIRTGPU_EXECBUF_FENCE_FD_IN;
+ eb.fence_fd = cbuf->in_fence_fd;
+ }
- if (in_fence_fd != -1) {
- eb.flags |= VIRTGPU_EXECBUF_FENCE_FD_IN;
- eb.fence_fd = in_fence_fd;
+ if (out_fence_fd != NULL)
+ eb.flags |= VIRTGPU_EXECBUF_FENCE_FD_OUT;
+ } else {
+ assert(cbuf->in_fence_fd < 0);
+ assert(out_fence_fd == NULL);
}
- if (out_fence_fd != NULL)
- eb.flags |= VIRTGPU_EXECBUF_FENCE_FD_OUT;
-
ret = drmIoctl(qdws->fd, DRM_IOCTL_VIRTGPU_EXECBUFFER, &eb);
if (ret == -1)
fprintf(stderr,"got error from kernel - expect bad rendering %d\n", errno);
cbuf->base.cdw = 0;
+ if (qws->supports_fences) {
+ if (cbuf->in_fence_fd >= 0) {
+ close(cbuf->in_fence_fd);
+ cbuf->in_fence_fd = -1;
+ }
+ }
+
if (out_fence_fd != NULL)
*out_fence_fd = eb.fence_fd;
}
static void virgl_fence_server_sync(struct virgl_winsys *vws,
- struct virgl_cmd_buf *cbuf,
+ struct virgl_cmd_buf *_cbuf,
struct pipe_fence_handle *fence)
{
+ struct virgl_drm_cmd_buf *cbuf = virgl_drm_cmd_buf(_cbuf);
struct virgl_hw_res *hw_res = virgl_hw_res(fence);
/* if not an external fence, then nothing more to do without preemption: */
}
cbuf->ws = vws;
cbuf->base.buf = cbuf->buf;
- cbuf->base.in_fence_fd = -1;
return &cbuf->base;
}
static int virgl_vtest_winsys_submit_cmd(struct virgl_winsys *vws,
struct virgl_cmd_buf *_cbuf,
- int in_fence_fd, int *out_fence_fd)
+ int *out_fence_fd)
{
struct virgl_vtest_winsys *vtws = virgl_vtest_winsys(vws);
struct virgl_vtest_cmd_buf *cbuf = virgl_vtest_cmd_buf(_cbuf);
if (cbuf->base.cdw == 0)
return 0;
- assert(in_fence_fd == -1);
assert(out_fence_fd == NULL);
ret = virgl_vtest_submit_cmd(vtws, cbuf);