i965: Hook up the MCS buffers in SURFACE_STATE on Broadwell.

MCS buffers are never allocated on Broadwell, so this does nothing for
now, but puts the infrastructure in place for when they do exist.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 0268e5c70a8867a309e3a7540801e9e3b8ee0f9b..72983f54ffdc4b50b3b17c8bf7213501b95e812a 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -157,6 +157,11 @@ gen8_update_texture_surface(struct gl_context *ctx,
       pitch = mt->pitch;
    }
 
+   if (mt->mcs_mt) {
+      aux_mt = mt->mcs_mt;
+      aux_mode = GEN8_SURFACE_AUX_MODE_MCS;
+   }
+
    /* If this is a view with restricted NumLayers, then our effective depth
     * is not just the miptree depth.
     */
@@ -355,6 +360,11 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
                        __FUNCTION__, _mesa_get_format_name(rb_format));
    }
 
+   if (mt->mcs_mt) {
+      aux_mt = mt->mcs_mt;
+      aux_mode = GEN8_SURFACE_AUX_MODE_MCS;
+   }
+
    uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 13 * 4, 64,
                                     &brw->wm.base.surf_offset[surf_index]);