(no commit message)

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 4ef3ab8808a26842e5f42581c8ad7d5b42b32430..8f44c94bb6804999d92fd5d8e85da8c0c80ab636 100644 (file)
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -798,9 +798,8 @@ Fields:
 * ew=8/16/32 - element width
 * sew=8/16/32 - source element width
 * vec=2/3/4 - SUBVL
-* mode=reduce/satu/sats/crpred
+* mode=mr/satu/sats/crpred
 * pred=1\<\<3/r3/~r3/r10/~r10/r30/~r30/lt/gt/le/ge/eq/ne
-* spred={reg spec}
 
 similar to x86 "rex" prefix.
 
@@ -828,11 +827,11 @@ Qualifiers:
 For modes:
 
 * pred-result:
-  - pm=lt/gt/le/ge/eq/ne/so/ns OR
-  - pm=RC1 OR pm=~RC1
+  - pm=lt/gt/le/ge/eq/ne/so/ns
+  - RC1 mode
 * fail-first
-  - ff=lt/gt/le/ge/eq/ne/so/ns OR
-  - ff=RC1 OR ff=~RC1
+  - ff=lt/gt/le/ge/eq/ne/so/ns
+  - RC1 mode
 * saturation:
   - sats
   - satu
@@ -1032,7 +1031,8 @@ be applied to a single instruction at a time, and SVP64 is based on
 the principle of strict Program Order even at the element
 level.  Thus it becomes
 necessary to add explicit more complex single instructions with
-more operands than would normally be seen in another ISA. If it
+more operands than would normally be seen in the average RISC ISA
+(3-in, 2-out, in some cases). If it
 was not for Power ISA already having LD/ST with update as well as
 Condition Codes and `lq` this would be hard to justify.