Remove bogus patch.

	* config/ia64/lib1funcs.asm: Revert 2001-07-02 change.
	* config/ia64/t-ia64: Likewise.
	(LIB1ASMFUNCS): Update comment.

From-SVN: r43796

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 0099e9609fe4c6a0118521b49e8324fe4518c805..5b415e98a37530ba5903a665119170a68615b74b 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2001-07-05  Jim Wilson  <wilson@redhat.com>
+
+       * config/ia64/lib1funcs.asm: Revert 2001-07-02 change.
+       * config/ia64/t-ia64: Likewise.
+       (LIB1ASMFUNCS): Update comment.
+
 2001-07-05  David Edelsohn  <edelsohn@gnu.org>
 
        * doc/install.texi (Install GCC: Binaries): Fix typo.

diff --git a/gcc/config/ia64/lib1funcs.asm b/gcc/config/ia64/lib1funcs.asm
index a69cef2713f0f42ff7538ebfa17986d124b73970..75e79b0a0f73e7044909ffc44697fcb8a3b31142 100644 (file)
--- a/gcc/config/ia64/lib1funcs.asm
+++ b/gcc/config/ia64/lib1funcs.asm
@@ -1,4 +1,4 @@
-#ifdef L_divtf3
+#ifdef L__divtf3
 // Compute a 80-bit IEEE double-extended quotient.
 //
 // From the Intel IA-64 Optimization Guide, choose the minimum latency
@@ -40,7 +40,7 @@ __divtf3:
        .endp __divtf3
 #endif
 
-#ifdef L_divdf3
+#ifdef L__divdf3
 // Compute a 64-bit IEEE double quotient.
 //
 // From the Intel IA-64 Optimization Guide, choose the minimum latency
@@ -82,7 +82,7 @@ __divdf3:
        .endp __divdf3
 #endif
 
-#ifdef L_divsf3
+#ifdef L__divsf3
 // Compute a 32-bit IEEE float quotient.
 //
 // From the Intel IA-64 Optimization Guide, choose the minimum latency
@@ -118,7 +118,7 @@ __divsf3:
        .endp __divsf3
 #endif
 
-#ifdef L_divdi3
+#ifdef L__divdi3
 // Compute a 64-bit integer quotient.
 //
 // From the Intel IA-64 Optimization Guide, choose the minimum latency
@@ -168,7 +168,7 @@ __divdi3:
        .endp __divdi3
 #endif
 
-#ifdef L_moddi3
+#ifdef L__moddi3
 // Compute a 64-bit integer modulus.
 //
 // From the Intel IA-64 Optimization Guide, choose the minimum latency
@@ -222,7 +222,7 @@ __moddi3:
        .endp __moddi3
 #endif
 
-#ifdef L_udivdi3
+#ifdef L__udivdi3
 // Compute a 64-bit unsigned integer quotient.
 //
 // From the Intel IA-64 Optimization Guide, choose the minimum latency
@@ -272,7 +272,7 @@ __udivdi3:
        .endp __udivdi3
 #endif
 
-#ifdef L_umoddi3
+#ifdef L__umoddi3
 // Compute a 64-bit unsigned integer modulus.
 //
 // From the Intel IA-64 Optimization Guide, choose the minimum latency
@@ -327,7 +327,7 @@ __umoddi3:
        .endp __umoddi3
 #endif
 
-#ifdef L_divsi3
+#ifdef L__divsi3
 // Compute a 32-bit integer quotient.
 //
 // From the Intel IA-64 Optimization Guide, choose the minimum latency
@@ -370,7 +370,7 @@ __divsi3:
        .endp __divsi3
 #endif
 
-#ifdef L_modsi3
+#ifdef L__modsi3
 // Compute a 32-bit integer modulus.
 //
 // From the Intel IA-64 Optimization Guide, choose the minimum latency
@@ -417,7 +417,7 @@ __modsi3:
        .endp __modsi3
 #endif
 
-#ifdef L_udivsi3
+#ifdef L__udivsi3
 // Compute a 32-bit unsigned integer quotient.
 //
 // From the Intel IA-64 Optimization Guide, choose the minimum latency
@@ -460,7 +460,7 @@ __udivsi3:
        .endp __udivsi3
 #endif
 
-#ifdef L_umodsi3
+#ifdef L__umodsi3
 // Compute a 32-bit unsigned integer modulus.
 //
 // From the Intel IA-64 Optimization Guide, choose the minimum latency
@@ -507,7 +507,7 @@ __umodsi3:
        .endp __umodsi3
 #endif
 
-#ifdef L_save_stack_nonlocal
+#ifdef L__save_stack_nonlocal
 // Notes on save/restore stack nonlocal: We read ar.bsp but write
 // ar.bspstore.  This is because ar.bsp can be read at all times
 // (independent of the RSE mode) but since it's read-only we need to
@@ -556,7 +556,7 @@ __ia64_save_stack_nonlocal:
        .endp __ia64_save_stack_nonlocal
 #endif
 
-#ifdef L_nonlocal_goto
+#ifdef L__nonlocal_goto
 // void __ia64_nonlocal_goto(void *target_label, void *save_area,
 //                          void *static_chain);
 
@@ -609,7 +609,7 @@ __ia64_nonlocal_goto:
        .endp __ia64_nonlocal_goto
 #endif
 
-#ifdef L_restore_stack_nonlocal
+#ifdef L__restore_stack_nonlocal
 // This is mostly the same as nonlocal_goto above.
 // ??? This has not been tested yet.
 
@@ -662,7 +662,7 @@ __ia64_restore_stack_nonlocal:
        .endp __ia64_restore_stack_nonlocal
 #endif
 
-#ifdef L_trampoline
+#ifdef L__trampoline
 // Implement the nested function trampoline.  This is out of line
 // so that we don't have to bother with flushing the icache, as
 // well as making the on-stack trampoline smaller.

diff --git a/gcc/config/ia64/t-ia64 b/gcc/config/ia64/t-ia64
index 69e2a49ac50608c60e0f8690b6387e38a9fa1e06..c413b03d66d455b7cc5ad21832f33e5e061a3395 100644 (file)
--- a/gcc/config/ia64/t-ia64
+++ b/gcc/config/ia64/t-ia64
@@ -1,9 +1,14 @@
 LIB1ASMSRC    = ia64/lib1funcs.asm
 
-LIB1ASMFUNCS  = _divtf3 _divdf3 _divsf3 \
-       _divdi3 _moddi3 _udivdi3 _umoddi3 \
-       _divsi3 _modsi3 _udivsi3 _umodsi3 _save_stack_nonlocal \
-       _nonlocal_goto _restore_stack_nonlocal _trampoline
+# We use different names for the DImode div/mod files so that they won't
+# conflict with libgcc2.c files.  We used to use __ia64 as a prefix, now
+# we use __ as the prefix.  Note that L_divdi3 in libgcc2.c actually defines
+# a TImode divide function, so there is no actual overlap here between
+# libgcc2.c and lib1funcs.asm.
+LIB1ASMFUNCS  = __divtf3 __divdf3 __divsf3 \
+       __divdi3 __moddi3 __udivdi3 __umoddi3 \
+       __divsi3 __modsi3 __udivsi3 __umodsi3 __save_stack_nonlocal \
+       __nonlocal_goto __restore_stack_nonlocal __trampoline
 
 # ??? Hack to get -P option used when compiling lib1funcs.asm, because Intel
 # assembler does not accept # line number as a comment.