targets/xilinx: remove keep attribute on clock going to idelayctrl

Causes P&R issues with Vivado.

diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py
index c6e90e45ef8ba123a77b7c1a27e7e959e94cd08a..ba058c5f5209fbc53212eaf59f402c6bacd6d3b0 100755 (executable)
--- a/litex/boards/targets/arty.py
+++ b/litex/boards/targets/arty.py
@@ -31,7 +31,6 @@ class _CRG(Module):
         self.cd_sys.clk.attr.add("keep")
         self.cd_sys4x.clk.attr.add("keep")
         self.cd_sys4x_dqs.clk.attr.add("keep")
-        self.cd_clk200.clk.attr.add("keep")
 
         self.submodules.pll = pll = S7PLL(speedgrade=-1)
         self.comb += pll.reset.eq(~platform.request("cpu_reset"))

diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py
index 7c8c331b7a26ec516e819d5d6f92894eda578464..efd739795d52af2402030e8635db1ee303bcaa6b 100755 (executable)
--- a/litex/boards/targets/genesys2.py
+++ b/litex/boards/targets/genesys2.py
@@ -29,7 +29,6 @@ class _CRG(Module):
 
         self.cd_sys.clk.attr.add("keep")
         self.cd_sys4x.clk.attr.add("keep")
-        self.cd_clk200.clk.attr.add("keep")
 
         self.submodules.pll = pll = S7MMCM(speedgrade=-2)
         self.comb += pll.reset.eq(~platform.request("cpu_reset_n"))

diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py
index 3ad91e76d774908cc45a3686af6a38f8364d82e2..14b53239c3034ff62a9ef0d51bf5ff1f79b34373 100755 (executable)
--- a/litex/boards/targets/kc705.py
+++ b/litex/boards/targets/kc705.py
@@ -29,7 +29,6 @@ class _CRG(Module):
 
         self.cd_sys.clk.attr.add("keep")
         self.cd_sys4x.clk.attr.add("keep")
-        self.cd_clk200.clk.attr.add("keep")
 
         self.submodules.pll = pll = S7MMCM(speedgrade=-2)
         self.comb += pll.reset.eq(platform.request("cpu_reset"))

diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py
index d676cff3d45e0f4215d1944a537c5193f105509b..06eda9e2e7500260cce0f2dafc1c7c6e066aac0b 100755 (executable)
--- a/litex/boards/targets/kcu105.py
+++ b/litex/boards/targets/kcu105.py
@@ -30,8 +30,6 @@ class _CRG(Module):
 
         self.cd_sys.clk.attr.add("keep")
         self.cd_sys4x.clk.attr.add("keep")
-        self.cd_clk200.clk.attr.add("keep")
-        self.cd_ic.clk.attr.add("keep")
 
         self.submodules.pll = pll = USMMCM(speedgrade=-2)
         self.comb += pll.reset.eq(platform.request("cpu_reset"))

diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py
index 661aba1826228b223d25f920b0fa660897751fcc..5adf51d8d2d9f83840057cf41726582869c53a5d 100755 (executable)
--- a/litex/boards/targets/nexys4ddr.py
+++ b/litex/boards/targets/nexys4ddr.py
@@ -23,15 +23,12 @@ class _CRG(Module):
         self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
         self.clock_domains.cd_sys2x_dqs = ClockDomain(reset_less=True)
         self.clock_domains.cd_clk200 = ClockDomain()
-        self.clock_domains.cd_clk100 = ClockDomain()
 
         # # #
 
         self.cd_sys.clk.attr.add("keep")
         self.cd_sys2x.clk.attr.add("keep")
         self.cd_sys2x_dqs.clk.attr.add("keep")
-        self.cd_clk200.clk.attr.add("keep")
-        self.cd_clk100.clk.attr.add("keep")
 
         self.submodules.pll = pll = S7MMCM(speedgrade=-1)
         self.comb += pll.reset.eq(~platform.request("cpu_reset"))
@@ -40,7 +37,6 @@ class _CRG(Module):
         pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
         pll.create_clkout(self.cd_sys2x_dqs, 2*sys_clk_freq, phase=90)
         pll.create_clkout(self.cd_clk200, 200e6)
-        pll.create_clkout(self.cd_clk100, 100e6)
 
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
 

diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py
index 1e58f831fb0b9581b248856efb3188416e27b6b6..d949f57af121fb281e525858f3774a3737f3ccbd 100755 (executable)
--- a/litex/boards/targets/nexys_video.py
+++ b/litex/boards/targets/nexys_video.py
@@ -32,8 +32,6 @@ class _CRG(Module):
         self.cd_sys.clk.attr.add("keep")
         self.cd_sys4x.clk.attr.add("keep")
         self.cd_sys4x_dqs.clk.attr.add("keep")
-        self.cd_clk200.clk.attr.add("keep")
-        self.cd_clk100.clk.attr.add("keep")
 
         self.submodules.pll = pll = S7MMCM(speedgrade=-1)
         self.comb += pll.reset.eq(~platform.request("cpu_reset"))
@@ -42,7 +40,6 @@ class _CRG(Module):
         pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
         pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
         pll.create_clkout(self.cd_clk200, 200e6)
-        pll.create_clkout(self.cd_clk100, 100e6)
 
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)