gcc/ChangeLog
2018-07-19 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_simd_mov<VQ:mode>): Replace
Umq with Umn.
(store_pair_lanes<mode>): Likewise.
* config/aarch64/aarch64-protos.h (aarch64_addr_query_type): Add new
enum value 'ADDR_QUERY_LDP_STP_N'.
* config/aarch64/aarch64.c (aarch64_addr_query_type): Likewise.
(aarch64_print_address_internal): Add declaration.
(aarch64_print_ldpstp_address): Remove.
(aarch64_classify_address): Adapt mode for 'ADDR_QUERY_LDP_STP_N'.
(aarch64_print_operand): Change printing of 'y'.
* config/aarch64/predicates.md (aarch64_mem_pair_lanes_operand): Use
new enum value 'ADDR_QUERY_LDP_STP_N', don't hardcode mode and use
'true' rather than '1'.
* gcc/config/aarch64/constraints.md (Uml): Likewise.
(Uml): Rename to Umn.
(Umq): Remove.
From-SVN: r262880
+2018-07-19 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/aarch64/aarch64-simd.md (aarch64_simd_mov<VQ:mode>): Replace
+ Umq with Umn.
+ (store_pair_lanes<mode>): Likewise.
+ * config/aarch64/aarch64-protos.h (aarch64_addr_query_type): Add new
+ enum value 'ADDR_QUERY_LDP_STP_N'.
+ * config/aarch64/aarch64.c (aarch64_addr_query_type): Likewise.
+ (aarch64_print_address_internal): Add declaration.
+ (aarch64_print_ldpstp_address): Remove.
+ (aarch64_classify_address): Adapt mode for 'ADDR_QUERY_LDP_STP_N'.
+ (aarch64_print_operand): Change printing of 'y'.
+ * config/aarch64/predicates.md (aarch64_mem_pair_lanes_operand): Use
+ new enum value 'ADDR_QUERY_LDP_STP_N', don't hardcode mode and use
+ 'true' rather than '1'.
+ * gcc/config/aarch64/constraints.md (Uml): Likewise.
+ (Uml): Rename to Umn.
+ (Umq): Remove.
+
2018-07-19 Richard Biener <rguenther@suse.de>
* tree-ssa-sccvn.h (struct vn_phi_s): Make phiargs member
ADDR_QUERY_LDP_STP
Query what is valid for a load/store pair.
+ ADDR_QUERY_LDP_STP_N
+ Query what is valid for a load/store pair, but narrow the incoming mode
+ for address checking. This is used for the store_pair_lanes patterns.
+
ADDR_QUERY_ANY
Query what is valid for at least one memory constraint, which may
allow things that "m" doesn't. For example, the SVE LDR and STR
enum aarch64_addr_query_type {
ADDR_QUERY_M,
ADDR_QUERY_LDP_STP,
+ ADDR_QUERY_LDP_STP_N,
ADDR_QUERY_ANY
};
(define_insn "*aarch64_simd_mov<VQ:mode>"
[(set (match_operand:VQ 0 "nonimmediate_operand"
- "=w, Umq, m, w, ?r, ?w, ?r, w")
+ "=w, Umn, m, w, ?r, ?w, ?r, w")
(match_operand:VQ 1 "general_operand"
"m, Dz, w, w, w, r, r, Dn"))]
"TARGET_SIMD
)
(define_insn "store_pair_lanes<mode>"
- [(set (match_operand:<VDBL> 0 "aarch64_mem_pair_lanes_operand" "=Uml, Uml")
+ [(set (match_operand:<VDBL> 0 "aarch64_mem_pair_lanes_operand" "=Umn, Umn")
(vec_concat:<VDBL>
(match_operand:VDC 1 "register_operand" "w, r")
(match_operand:VDC 2 "register_operand" "w, r")))]
int misalignment,
bool is_packed);
static machine_mode aarch64_simd_container_mode (scalar_mode, poly_int64);
-static bool aarch64_print_ldpstp_address (FILE *, machine_mode, rtx);
+static bool aarch64_print_address_internal (FILE*, machine_mode, rtx,
+ aarch64_addr_query_type);
/* Major revision number of the ARM Architecture implemented by the target. */
unsigned aarch64_architecture_version;
unsigned int vec_flags = aarch64_classify_vector_mode (mode);
bool advsimd_struct_p = (vec_flags == (VEC_ADVSIMD | VEC_STRUCT));
bool load_store_pair_p = (type == ADDR_QUERY_LDP_STP
+ || type == ADDR_QUERY_LDP_STP_N
|| mode == TImode
|| mode == TFmode
|| (BYTES_BIG_ENDIAN && advsimd_struct_p));
+ /* If we are dealing with ADDR_QUERY_LDP_STP_N that means the incoming mode
+ corresponds to the actual size of the memory being loaded/stored and the
+ mode of the corresponding addressing mode is half of that. */
+ if (type == ADDR_QUERY_LDP_STP_N
+ && known_eq (GET_MODE_SIZE (mode), 16))
+ mode = DFmode;
+
bool allow_reg_index_p = (!load_store_pair_p
&& (known_lt (GET_MODE_SIZE (mode), 16)
|| vec_flags == VEC_ADVSIMD
return;
}
- if (code == 'y')
- /* LDP/STP which uses a single double-width memory operand.
- Adjust the mode to appear like a typical LDP/STP.
- Currently this is supported for 16-byte accesses only. */
- mode = DFmode;
-
- if (!aarch64_print_ldpstp_address (f, mode, XEXP (x, 0)))
+ if (!aarch64_print_address_internal (f, mode, XEXP (x, 0),
+ code == 'y'
+ ? ADDR_QUERY_LDP_STP_N
+ : ADDR_QUERY_LDP_STP))
output_operand_lossage ("invalid operand prefix '%%%c'", code);
}
break;
return false;
}
-/* Print address 'x' of a LDP/STP with mode 'mode'. */
-static bool
-aarch64_print_ldpstp_address (FILE *f, machine_mode mode, rtx x)
-{
- return aarch64_print_address_internal (f, mode, x, ADDR_QUERY_LDP_STP);
-}
-
/* Print address 'x' of a memory access with mode 'mode'. */
static void
aarch64_print_operand_address (FILE *f, machine_mode mode, rtx x)
(and (match_code "mem")
(match_test "REG_P (XEXP (op, 0))")))
-(define_memory_constraint "Umq"
- "@internal
- A memory address which uses a base register with an offset small enough for
- a load/store pair operation in DI mode."
- (and (match_code "mem")
- (match_test "aarch64_legitimate_address_p (DImode, XEXP (op, 0), false,
- ADDR_QUERY_LDP_STP)")))
-
(define_memory_constraint "Ump"
"@internal
A memory address suitable for a load/store pair operation."
(match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
true, ADDR_QUERY_LDP_STP)")))
-;; Used for storing two 64-bit values in an AdvSIMD register using an STP
-;; as a 128-bit vec_concat.
-(define_memory_constraint "Uml"
+;; Used for storing or loading pairs in an AdvSIMD register using an STP/LDP
+;; as a vector-concat. The address mode uses the same constraints as if it
+;; were for a single value.
+(define_memory_constraint "Umn"
"@internal
A memory address suitable for a load/store pair operation."
(and (match_code "mem")
- (match_test "aarch64_legitimate_address_p (DFmode, XEXP (op, 0), 1,
- ADDR_QUERY_LDP_STP)")))
+ (match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
+ true,
+ ADDR_QUERY_LDP_STP_N)")))
(define_memory_constraint "Utr"
"@internal
;; as a 128-bit vec_concat.
(define_predicate "aarch64_mem_pair_lanes_operand"
(and (match_code "mem")
- (match_test "aarch64_legitimate_address_p (DFmode, XEXP (op, 0), 1,
- ADDR_QUERY_LDP_STP)")))
+ (match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
+ true,
+ ADDR_QUERY_LDP_STP_N)")))
(define_predicate "aarch64_prefetch_operand"
(match_test "aarch64_address_valid_for_prefetch_p (op, false)"))
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