--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 49036 # Simulator instruction rate (inst/s)
+host_mem_usage 153428 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
+host_tick_rate 135151055 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 5024 # Number of instructions simulated
+sim_seconds 0.000014 # Number of seconds simulated
+sim_ticks 13881500 # Number of ticks simulated
+system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.BPredUnit.BTBHits 549 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 1924 # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect 53 # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect 721 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 1540 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 2339 # Number of BP lookups
+system.cpu.BPredUnit.usedRAS 384 # Number of times the RAS was used to get a target.
+system.cpu.commit.COM:branches 879 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 63 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle::samples 14165
+system.cpu.commit.COM:committed_per_cycle::min_value 0
+system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00%
+system.cpu.commit.COM:committed_per_cycle::0-1 11701 82.61%
+system.cpu.commit.COM:committed_per_cycle::1-2 1166 8.23%
+system.cpu.commit.COM:committed_per_cycle::2-3 493 3.48%
+system.cpu.commit.COM:committed_per_cycle::3-4 279 1.97%
+system.cpu.commit.COM:committed_per_cycle::4-5 290 2.05%
+system.cpu.commit.COM:committed_per_cycle::5-6 74 0.52%
+system.cpu.commit.COM:committed_per_cycle::6-7 61 0.43%
+system.cpu.commit.COM:committed_per_cycle::7-8 38 0.27%
+system.cpu.commit.COM:committed_per_cycle::8 63 0.44%
+system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00%
+system.cpu.commit.COM:committed_per_cycle::total 14165
+system.cpu.commit.COM:committed_per_cycle::max_value 8
+system.cpu.commit.COM:committed_per_cycle::mean 0.399223
+system.cpu.commit.COM:committed_per_cycle::stdev 1.126414
+system.cpu.commit.COM:count 5655 # Number of instructions committed
+system.cpu.commit.COM:loads 1130 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 2054 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 604 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 5655 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 15 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 5936 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 5024 # Number of Instructions Simulated
+system.cpu.committedInsts_total 5024 # Number of Instructions Simulated
+system.cpu.cpi 5.526274 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 5.526274 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 2286 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 33976.377953 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36034.883721 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 2159 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 4315000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.055556 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 127 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 41 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 3099000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.037620 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 86 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 27701.724138 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36093.750000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 634 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 8033500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.313853 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 290 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 226 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 2310000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.069264 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 20.970370 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.demand_accesses 3210 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 29612.709832 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 36060 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 2793 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 12348500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.129907 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 417 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 267 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 5409000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.046729 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 150 # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses 3210 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 29612.709832 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 36060 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 2793 # number of overall hits
+system.cpu.dcache.overall_miss_latency 12348500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.129907 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 417 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 267 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 5409000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.046729 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 150 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse 87.531358 # Cycle average of tags in use
+system.cpu.dcache.total_refs 2831 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 0 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 479 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 128 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 128 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 14141 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 9863 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 3823 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 1052 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 251 # Number of squashed instructions handled by decode
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.fetch.Branches 2339 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 2162 # Number of cache lines fetched
+system.cpu.fetch.Cycles 6161 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 360 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 15261 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 737 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.084246 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 2162 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 933 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 0.549669 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 15217
+system.cpu.fetch.rateDist::min_value 0
+system.cpu.fetch.rateDist::underflows 0 0.00%
+system.cpu.fetch.rateDist::0-1 11225 73.77%
+system.cpu.fetch.rateDist::1-2 1766 11.61%
+system.cpu.fetch.rateDist::2-3 196 1.29%
+system.cpu.fetch.rateDist::3-4 137 0.90%
+system.cpu.fetch.rateDist::4-5 314 2.06%
+system.cpu.fetch.rateDist::5-6 113 0.74%
+system.cpu.fetch.rateDist::6-7 304 2.00%
+system.cpu.fetch.rateDist::7-8 249 1.64%
+system.cpu.fetch.rateDist::8 913 6.00%
+system.cpu.fetch.rateDist::overflows 0 0.00%
+system.cpu.fetch.rateDist::total 15217
+system.cpu.fetch.rateDist::max_value 8
+system.cpu.fetch.rateDist::mean 1.002892
+system.cpu.fetch.rateDist::stdev 2.262712
+system.cpu.icache.ReadReq_accesses 2162 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 35500 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34915.151515 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 1731 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 15300500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.199352 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 431 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 101 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 11522000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.152636 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 330 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 5.245455 # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.icache.cache_copies 0 # number of cache copies performed
+system.cpu.icache.demand_accesses 2162 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 35500 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34915.151515 # average overall mshr miss latency
+system.cpu.icache.demand_hits 1731 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 15300500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.199352 # miss rate for demand accesses
+system.cpu.icache.demand_misses 431 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 101 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 11522000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.152636 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 330 # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes 0 # number of fast writes performed
+system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses 2162 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 35500 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34915.151515 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 1731 # number of overall hits
+system.cpu.icache.overall_miss_latency 15300500 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.199352 # miss rate for overall accesses
+system.cpu.icache.overall_misses 431 # number of overall misses
+system.cpu.icache.overall_mshr_hits 101 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 11522000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.152636 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 330 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.icache.replacements 16 # number of replacements
+system.cpu.icache.sampled_refs 330 # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse 158.760808 # Cycle average of tags in use
+system.cpu.icache.total_refs 1731 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 0 # number of writebacks
+system.cpu.idleCycles 12547 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 1206 # Number of branches executed
+system.cpu.iew.EXEC:nop 1806 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.291349 # Inst execution rate
+system.cpu.iew.EXEC:refs 3420 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 1048 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 4016 # num instructions consuming a value
+system.cpu.iew.WB:count 7315 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.694970 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 2791 # num instructions producing a value
+system.cpu.iew.WB:rate 0.263471 # insts written-back per cycle
+system.cpu.iew.WB:sent 7402 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 661 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 8 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 2783 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 15 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 968 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 1158 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 11594 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 2372 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 531 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 8089 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 1052 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 68 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation 22 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 1653 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 234 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 276 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 385 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.180954 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.180954 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 8620 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.start_dist
+ No_OpClass 0 0.00% # Type of FU issued
+ IntAlu 4988 57.87% # Type of FU issued
+ IntMult 5 0.06% # Type of FU issued
+ IntDiv 2 0.02% # Type of FU issued
+ FloatAdd 2 0.02% # Type of FU issued
+ FloatCmp 0 0.00% # Type of FU issued
+ FloatCvt 0 0.00% # Type of FU issued
+ FloatMult 0 0.00% # Type of FU issued
+ FloatDiv 0 0.00% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 2560 29.70% # Type of FU issued
+ MemWrite 1063 12.33% # Type of FU issued
+ IprAccess 0 0.00% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.end_dist
+system.cpu.iq.ISSUE:fu_busy_cnt 162 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.018794 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full.start_dist
+ No_OpClass 0 0.00% # attempts to use FU when none available
+ IntAlu 10 6.17% # attempts to use FU when none available
+ IntMult 0 0.00% # attempts to use FU when none available
+ IntDiv 0 0.00% # attempts to use FU when none available
+ FloatAdd 0 0.00% # attempts to use FU when none available
+ FloatCmp 0 0.00% # attempts to use FU when none available
+ FloatCvt 0 0.00% # attempts to use FU when none available
+ FloatMult 0 0.00% # attempts to use FU when none available
+ FloatDiv 0 0.00% # attempts to use FU when none available
+ FloatSqrt 0 0.00% # attempts to use FU when none available
+ MemRead 98 60.49% # attempts to use FU when none available
+ MemWrite 54 33.33% # attempts to use FU when none available
+ IprAccess 0 0.00% # attempts to use FU when none available
+ InstPrefetch 0 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full.end_dist
+system.cpu.iq.ISSUE:issued_per_cycle::samples 15217
+system.cpu.iq.ISSUE:issued_per_cycle::min_value 0
+system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00%
+system.cpu.iq.ISSUE:issued_per_cycle::0-1 11370 74.72%
+system.cpu.iq.ISSUE:issued_per_cycle::1-2 1673 10.99%
+system.cpu.iq.ISSUE:issued_per_cycle::2-3 787 5.17%
+system.cpu.iq.ISSUE:issued_per_cycle::3-4 717 4.71%
+system.cpu.iq.ISSUE:issued_per_cycle::4-5 332 2.18%
+system.cpu.iq.ISSUE:issued_per_cycle::5-6 198 1.30%
+system.cpu.iq.ISSUE:issued_per_cycle::6-7 91 0.60%
+system.cpu.iq.ISSUE:issued_per_cycle::7-8 34 0.22%
+system.cpu.iq.ISSUE:issued_per_cycle::8 15 0.10%
+system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00%
+system.cpu.iq.ISSUE:issued_per_cycle::total 15217
+system.cpu.iq.ISSUE:issued_per_cycle::max_value 8
+system.cpu.iq.ISSUE:issued_per_cycle::mean 0.566472
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.217507
+system.cpu.iq.ISSUE:rate 0.310474 # Inst issue rate
+system.cpu.iq.iqInstsAdded 9773 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 8620 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 15 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 4182 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 30 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedOperandsExamined 2741 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.l2cache.ReadExReq_accesses 49 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34704.081633 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31408.163265 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 1700500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 49 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 1539000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 49 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 416 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34308.252427 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31129.854369 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 14135000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.990385 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 412 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 12825500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990385 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 412 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 34400 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31166.666667 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 516000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 467500 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 0.010076 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.demand_accesses 465 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34350.325380 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31159.436009 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 15835500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.991398 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 461 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency 14364500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.991398 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 461 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses 465 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34350.325380 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31159.436009 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 4 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 15835500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.991398 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 461 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency 14364500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.991398 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 461 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.sampled_refs 397 # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse 208.689672 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 0 # number of writebacks
+system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 2783 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1158 # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles 27764 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 20 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 3304 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IdleCycles 10242 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 16 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 15583 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 13384 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 8214 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 3446 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 1052 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 29 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 4910 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 428 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 20 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 125 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 14 # count of temporary serializing insts renamed
+system.cpu.timesIdled 249 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.workload.PROG:num_syscalls 13 # Number of system calls
+
+---------- End Simulation Statistics ----------
projects / gem5.git / commitdiff