LiteXXX cores: fix frequency print in test/test_regs.py

diff --git a/misoclib/com/liteeth/example_designs/test/test_regs.py b/misoclib/com/liteeth/example_designs/test/test_regs.py
index 3e41821fbd5fd9f752a768852903dfc62bc95e57..ea8767ac9554da4b64be9d8726e1527542b6b357 100644 (file)
--- a/misoclib/com/liteeth/example_designs/test/test_regs.py
+++ b/misoclib/com/liteeth/example_designs/test/test_regs.py
@@ -4,7 +4,7 @@ def main(wb):
        ###
        print("sysid     : 0x{:04x}".format(regs.identifier_sysid.read()))
        print("revision  : 0x{:04x}".format(regs.identifier_revision.read()))
-       print("frequency : 0x{:04x}MHz".format(int(regs.identifier_frequency.read()/1000000)))
+       print("frequency : {}MHz".format(int(regs.identifier_frequency.read()/1000000)))
        SRAM_BASE = 0x02000000
        wb.write(SRAM_BASE, [i for i in range(64)])
        print(wb.read(SRAM_BASE, 64))

diff --git a/misoclib/mem/litesata/example_designs/test/test_regs.py b/misoclib/mem/litesata/example_designs/test/test_regs.py
index eb30efbfb328697488343bd3f4e616c2f681d55e..07ee4915be649e076e2dfb7bff18de1579fac7e9 100644 (file)
--- a/misoclib/mem/litesata/example_designs/test/test_regs.py
+++ b/misoclib/mem/litesata/example_designs/test/test_regs.py
@@ -4,6 +4,6 @@ def main(wb):
        ###
        print("sysid     : 0x{:04x}".format(regs.identifier_sysid.read()))
        print("revision  : 0x{:04x}".format(regs.identifier_revision.read()))
-       print("frequency : 0x{:04x}MHz".format(int(regs.identifier_frequency.read()/1000000)))
+       print("frequency : {}MHz".format(int(regs.identifier_frequency.read()/1000000)))
        ###
        wb.close()

diff --git a/misoclib/tools/litescope/example_designs/test/test_regs.py b/misoclib/tools/litescope/example_designs/test/test_regs.py
index eb30efbfb328697488343bd3f4e616c2f681d55e..07ee4915be649e076e2dfb7bff18de1579fac7e9 100644 (file)
--- a/misoclib/tools/litescope/example_designs/test/test_regs.py
+++ b/misoclib/tools/litescope/example_designs/test/test_regs.py
@@ -4,6 +4,6 @@ def main(wb):
        ###
        print("sysid     : 0x{:04x}".format(regs.identifier_sysid.read()))
        print("revision  : 0x{:04x}".format(regs.identifier_revision.read()))
-       print("frequency : 0x{:04x}MHz".format(int(regs.identifier_frequency.read()/1000000)))
+       print("frequency : {}MHz".format(int(regs.identifier_frequency.read()/1000000)))
        ###
        wb.close()