Put abc_* attributes above port

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 2fcb0369edf1a0839bc4560f4d3a3f6c18f06496..dc8334acba1fae55eae2b6f2114addcb51e2dd21 100644 (file)
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -17,10 +17,12 @@ endmodule
 // ---------------------------------------
 (* abc_box_id=1, lib_whitebox *)
 module CCU2C(
-       (* abc_carry *) input CIN,
+       (* abc_carry *)
+       input  CIN,
        input  A0, B0, C0, D0, A1, B1, C1, D1,
        output S0, S1,
-       (* abc_carry *) output COUT
+       (* abc_carry *)
+       output COUT
 );
        parameter [15:0] INIT0 = 16'h0000;
        parameter [15:0] INIT1 = 16'h0000;
@@ -109,9 +111,12 @@ endmodule
 // ---------------------------------------
 //(* abc_box_id=2 *)
 module TRELLIS_DPR16X4 (
-       (* abc_scc_break *) input [3:0] DI,
-       (* abc_scc_break *) input [3:0] WAD,
-       (* abc_scc_break *) input       WRE,
+       (* abc_scc_break *)
+       input  [3:0] DI,
+       (* abc_scc_break *)
+       input  [3:0] WAD,
+       (* abc_scc_break *)
+       input        WRE,
        input        WCK,
        input  [3:0] RAD,
        output [3:0] DO

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index ab04808f4d33d1d85fe4f05c75dbb8742163c879..c7f3bdad255bb9b1675aedab5c5a2b10d0799cb6 100644 (file)
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -143,11 +143,13 @@ endmodule
 
 (* abc_box_id = 1, lib_whitebox *)
 module \$__ICE40_FULL_ADDER (
-       (* abc_carry *) output CO,
+       (* abc_carry *)
+       output CO,
        output O,
        input A,
        input B,
-       (* abc_carry *) input CI
+       (* abc_carry *)
+       input CI
 );
        SB_CARRY carry (
                .I0(A),

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index bec9ea1a0c783f56aec005dae8fc06e55467fca9..e3897d9a69f003ecd53e7675a0ab48208cca245d 100644 (file)
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -183,9 +183,11 @@ endmodule
 
 (* abc_box_id = 4, lib_whitebox *)
 module CARRY4(
-  (* abc_carry *) output [3:0] CO,
+  (* abc_carry *)
+  output [3:0] CO,
   output [3:0] O,
-  (* abc_carry *) input CI,
+  (* abc_carry *)
+  input        CI,
   input        CYINIT,
   input  [3:0] DI, S
 );
@@ -298,9 +300,11 @@ endmodule
 (* abc_box_id = 5 *)
 module RAM32X1D (
   output DPO, SPO,
-  (* abc_scc_break *) input D,
+  (* abc_scc_break *)
+  input  D,
   input  WCLK,
-  (* abc_scc_break *) input WE,
+  (* abc_scc_break *)
+  input  WE,
   input  A0, A1, A2, A3, A4,
   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
 );
@@ -318,7 +322,8 @@ endmodule
 (* abc_box_id = 6 *)
 module RAM64X1D (
   output DPO, SPO,
-  (* abc_scc_break *) input D,
+  (* abc_scc_break *)
+  input  D,
   input  WCLK,
   (* abc_scc_break *) input WE,
   input  A0, A1, A2, A3, A4, A5,
@@ -338,9 +343,11 @@ endmodule
 (* abc_box_id = 7 *)
 module RAM128X1D (
   output       DPO, SPO,
-  (* abc_scc_break *) input D,
+  (* abc_scc_break *)
+  input        D,
   input        WCLK,
-  (* abc_scc_break *) input WE,
+  (* abc_scc_break *)
+  input        WE,
   input  [6:0] A, DPRA
 );
   parameter INIT = 128'h0;