WIP -chparam support for hierarchy when verific

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index b191c910d315738c9c04d70ca17ca4610ba8b69e..58a29ada4339d8806d42a991903772946125d3f6 100644 (file)
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -775,15 +775,16 @@ void VerificImporter::merge_past_ffs(pool<RTLIL::Cell*> &candidates)
                merge_past_ffs_clock(it.second, it.first.first, it.first.second);
 }
 
-void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*> &nl_todo)
+void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*> &nl_todo, bool top)
 {
-       std::string module_name = nl->IsOperator() ? std::string("$verific$") + nl->Owner()->Name() : RTLIL::escape_id(nl->Owner()->Name());
+       std::string netlist_name = top ? nl->CellBaseName() : nl->Owner()->Name();
+       std::string module_name = nl->IsOperator() ? "$verific$" + netlist_name : RTLIL::escape_id(netlist_name);
 
        netlist = nl;
 
        if (design->has(module_name)) {
                if (!nl->IsOperator() && !is_blackbox(nl))
-                       log_cmd_error("Re-definition of module `%s'.\n", nl->Owner()->Name());
+                       log_cmd_error("Re-definition of module `%s'.\n", netlist_name.c_str());
                return;
        }
 
@@ -1753,7 +1754,7 @@ struct VerificExtNets
        }
 };
 
-void verific_import(Design *design, std::string top)
+void verific_import(Design *design, const std::map<std::string,std::string> &parameters, std::string top)
 {
        verific_sva_fsm_limit = 16;
 
@@ -1766,11 +1767,15 @@ void verific_import(Design *design, std::string top)
        if (vhdl_lib) vhdl_libs.InsertLast(vhdl_lib);
        if (veri_lib) veri_libs.InsertLast(veri_lib);
 
+       Map verific_params(STRING_HASH);
+       for (auto i : parameters)
+               verific_params.Insert(i.first.c_str(), i.second.c_str());
+
        if (top.empty()) {
-               netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs);
+               netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, &verific_params);
        }
        else {
-               const Map *tree_tops = hier_tree::CreateHierarchicalTreeAll(&veri_libs, &vhdl_libs);
+               const Map *tree_tops = hier_tree::CreateHierarchicalTreeAll(&veri_libs, &vhdl_libs, &verific_params);
                HierTreeNode *node = tree_tops ? static_cast<HierTreeNode*>(tree_tops->GetValue(top.c_str())) : NULL;
                if (node) {
                        Map specific_tops(STRING_HASH);
@@ -1795,7 +1800,7 @@ void verific_import(Design *design, std::string top)
        int i;
 
        FOREACH_ARRAY_ITEM(netlists, i, nl) {
-               if (top.empty() || nl->Owner()->Name() == top)
+               if (top.empty() || nl->CellBaseName() == top)
                        nl_todo.insert(nl);
        }
 
@@ -1812,7 +1817,7 @@ void verific_import(Design *design, std::string top)
                Netlist *nl = *nl_todo.begin();
                if (nl_done.count(nl) == 0) {
                        VerificImporter importer(false, false, false, false, false, false);
-                       importer.import_netlist(design, nl, nl_todo);
+                       importer.import_netlist(design, nl, nl_todo, nl->CellBaseName() == top);
                }
                nl_todo.erase(nl);
                nl_done.insert(nl);
@@ -2235,8 +2240,8 @@ struct VerificPass : public Pass {
                                        continue;
                                }
                                if (args[argidx] == "-chparam"  && argidx+2 < GetSize(args)) {
-                                        const std::string &key = args[++argidx];
-                                        const std::string &value = args[++argidx];
+                                       const std::string &key = args[++argidx];
+                                       const std::string &value = args[++argidx];
                                        unsigned new_insertion = parameters.Insert(key.c_str(), value.c_str(),
                                                                                   1 /* force_overwrite */);
                                        if (!new_insertion)

diff --git a/frontends/verific/verific.h b/frontends/verific/verific.h
index b331dd4b94db5f235e05383cc8b1b2ad41b8545c..fb44b17367f697a3765d30dd141f8fcca6dbc352 100644 (file)
--- a/frontends/verific/verific.h
+++ b/frontends/verific/verific.h
@@ -26,7 +26,7 @@ YOSYS_NAMESPACE_BEGIN
 extern int verific_verbose;
 
 extern bool verific_import_pending;
-extern void verific_import(Design *design, std::string top = std::string());
+extern void verific_import(Design *design, const std::map<std::string,std::string> &parameters, std::string top = std::string());
 
 extern pool<int> verific_sva_prims;
 
@@ -93,7 +93,7 @@ struct VerificImporter
        void merge_past_ffs_clock(pool<RTLIL::Cell*> &candidates, SigBit clock, bool clock_pol);
        void merge_past_ffs(pool<RTLIL::Cell*> &candidates);
 
-       void import_netlist(RTLIL::Design *design, Verific::Netlist *nl, std::set<Verific::Netlist*> &nl_todo);
+       void import_netlist(RTLIL::Design *design, Verific::Netlist *nl, std::set<Verific::Netlist*> &nl_todo, bool top=false);
 };
 
 void verific_import_sva_assert(VerificImporter *importer, Verific::Instance *inst);

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index b8ff99884b6e88cb4d4650eedd529c2a01bc4eb6..483b386e5768b2b950e39807aa8cb4108d02ebc3 100644 (file)
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -570,7 +570,7 @@ struct HierarchyPass : public Pass {
                log("\n");
                log("    -simcheck\n");
                log("        like -check, but also throw an error if blackbox modules are\n");
-               log("        instantiated, and throw an error if the design has no top module\n");
+               log("        instantiated, and throw an error if the design has no top module.\n");
                log("\n");
                log("    -purge_lib\n");
                log("        by default the hierarchy command will not remove library (blackbox)\n");
@@ -583,20 +583,20 @@ struct HierarchyPass : public Pass {
                log("\n");
                log("    -keep_positionals\n");
                log("        per default this pass also converts positional arguments in cells\n");
-               log("        to arguments using port names. this option disables this behavior.\n");
+               log("        to arguments using port names. This option disables this behavior.\n");
                log("\n");
                log("    -keep_portwidths\n");
                log("        per default this pass adjusts the port width on cells that are\n");
-               log("        module instances when the width does not match the module port. this\n");
+               log("        module instances when the width does not match the module port. This\n");
                log("        option disables this behavior.\n");
                log("\n");
                log("    -nokeep_asserts\n");
                log("        per default this pass sets the \"keep\" attribute on all modules\n");
-               log("        that directly or indirectly contain one or more $assert cells. this\n");
+               log("        that directly or indirectly contain one or more $assert cells. This\n");
                log("        option disables this behavior.\n");
                log("\n");
                log("    -top <module>\n");
-               log("        use the specified top module to built a design hierarchy. modules\n");
+               log("        use the specified top module to build the design hierarchy. Modules\n");
                log("        outside this tree (unused modules) are removed.\n");
                log("\n");
                log("        when the -top option is used, the 'top' attribute will be set on the\n");
@@ -606,6 +606,12 @@ struct HierarchyPass : public Pass {
                log("    -auto-top\n");
                log("        automatically determine the top of the design hierarchy and mark it.\n");
                log("\n");
+               log("    -chparam name value \n");
+               log("       elaborate the top module using this parameter value. Modules on which\n");
+               log("       this parameter does not exist may cause a warning message to be output.\n");
+               log("       This option can be specified multiple times to override multiple\n");
+               log("       parameters. String values must be passed in double quotes (\").\n");
+               log("\n");
                log("In -generate mode this pass generates blackbox modules for the given cell\n");
                log("types (wildcards supported). For this the design is searched for cells that\n");
                log("match the given types and then the given port declarations are used to\n");
@@ -641,6 +647,7 @@ struct HierarchyPass : public Pass {
                bool nokeep_asserts = false;
                std::vector<std::string> generate_cells;
                std::vector<generate_port_decl_t> generate_ports;
+               std::map<std::string, std::string> parameters;
 
                size_t argidx;
                for (argidx = 1; argidx < args.size(); argidx++)
@@ -729,6 +736,16 @@ struct HierarchyPass : public Pass {
                                auto_top_mode = true;
                                continue;
                        }
+                       if (args[argidx] == "-chparam"  && argidx+2 < args.size()) {
+                               const std::string &key = args[++argidx];
+                               const std::string &value = args[++argidx];
+                               auto r = parameters.emplace(key, value);
+                               if (!r.second) {
+                                       log_warning_noprefix("-chparam %s already specified: overwriting.\n", key.c_str());
+                                       r.first->second = value;
+                               }
+                               continue;
+                       }
                        break;
                }
                extra_args(args, argidx, design, false);
@@ -736,7 +753,7 @@ struct HierarchyPass : public Pass {
                if (!load_top_mod.empty()) {
 #ifdef YOSYS_ENABLE_VERIFIC
                        if (verific_import_pending) {
-                               verific_import(design, load_top_mod);
+                               verific_import(design, parameters, load_top_mod);
                                top_mod = design->module(RTLIL::escape_id(load_top_mod));
                        }
 #endif
@@ -745,7 +762,7 @@ struct HierarchyPass : public Pass {
                } else {
 #ifdef YOSYS_ENABLE_VERIFIC
                        if (verific_import_pending)
-                               verific_import(design);
+                               verific_import(design, parameters);
 #endif
                }