+2014-11-18 James Greenhalgh <james.greenhalgh@arm.com>
+
+ * config/arm/t-arm (arm.o): Include arm-protos.h in the recipe.
+ * config/arm/arm.c (FL_CO_PROC): Move to arm-protos.h.
+ (FL_ARCH3M): Likewise.
+ (FL_MODE26): Likewise.
+ (FL_MODE32): Likewise.
+ (FL_ARCH4): Likewise.
+ (FL_ARCH5): Likewise.
+ (FL_THUMB): Likewise.
+ (FL_LDSCHED): Likewise.
+ (FL_STRONG): Likewise.
+ (FL_ARCH5E): Likewise.
+ (FL_XSCALE): Likewise.
+ (FL_ARCH6): Likewise.
+ (FL_VFPV2): Likewise.
+ (FL_WBUF): Likewise.
+ (FL_ARCH6K): Likewise.
+ (FL_THUMB2): Likewise.
+ (FL_NOTM): Likewise.
+ (FL_THUMB_DIV): Likewise.
+ (FL_VFPV3): Likewise.
+ (FL_NEON): Likewise.
+ (FL_ARCH7EM): Likewise.
+ (FL_ARCH7): Likewise.
+ (FL_ARM_DIV): Likewise.
+ (FL_ARCH8): Likewise.
+ (FL_CRC32): Likewise.
+ (FL_SMALLMUL): Likewise.
+ (FL_IWMMXT): Likewise.
+ (FL_IWMMXT2): Likewise.
+ (FL_TUNE): Likewise.
+ (FL_FOR_ARCH2): Likewise.
+ (FL_FOR_ARCH3): Likewise.
+ (FL_FOR_ARCH3M): Likewise.
+ (FL_FOR_ARCH4): Likewise.
+ (FL_FOR_ARCH4T): Likewise.
+ (FL_FOR_ARCH5): Likewise.
+ (FL_FOR_ARCH5T): Likewise.
+ (FL_FOR_ARCH5E): Likewise.
+ (FL_FOR_ARCH5TE): Likewise.
+ (FL_FOR_ARCH5TEJ): Likewise.
+ (FL_FOR_ARCH6): Likewise.
+ (FL_FOR_ARCH6J): Likewise.
+ (FL_FOR_ARCH6K): Likewise.
+ (FL_FOR_ARCH6Z): Likewise.
+ (FL_FOR_ARCH6ZK): Likewise.
+ (FL_FOR_ARCH6T2): Likewise.
+ (FL_FOR_ARCH6M): Likewise.
+ (FL_FOR_ARCH7): Likewise.
+ (FL_FOR_ARCH7A): Likewise.
+ (FL_FOR_ARCH7VE): Likewise.
+ (FL_FOR_ARCH7R): Likewise.
+ (FL_FOR_ARCH7M): Likewise.
+ (FL_FOR_ARCH7EM): Likewise.
+ (FL_FOR_ARCH8A): Likewise.
+ * config/arm/arm-protos.h: Take definitions moved from arm.c.
+
2014-11-18 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/arm.c (arm_expand_neon_builtin): Remove "Magic Word"
extern bool arm_is_constant_pool_ref (rtx);
+/* Flags used to identify the presence of processor capabilities. */
+
+/* Bit values used to identify processor capabilities. */
+#define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
+#define FL_ARCH3M (1 << 1) /* Extended multiply */
+#define FL_MODE26 (1 << 2) /* 26-bit mode support */
+#define FL_MODE32 (1 << 3) /* 32-bit mode support */
+#define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
+#define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
+#define FL_THUMB (1 << 6) /* Thumb aware */
+#define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
+#define FL_STRONG (1 << 8) /* StrongARM */
+#define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
+#define FL_XSCALE (1 << 10) /* XScale */
+/* spare (1 << 11) */
+#define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
+ media instructions. */
+#define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
+#define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
+ Note: ARM6 & 7 derivatives only. */
+#define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */
+#define FL_THUMB2 (1 << 16) /* Thumb-2. */
+#define FL_NOTM (1 << 17) /* Instructions not present in the 'M'
+ profile. */
+#define FL_THUMB_DIV (1 << 18) /* Hardware divide (Thumb mode). */
+#define FL_VFPV3 (1 << 19) /* Vector Floating Point V3. */
+#define FL_NEON (1 << 20) /* Neon instructions. */
+#define FL_ARCH7EM (1 << 21) /* Instructions present in the ARMv7E-M
+ architecture. */
+#define FL_ARCH7 (1 << 22) /* Architecture 7. */
+#define FL_ARM_DIV (1 << 23) /* Hardware divide (ARM mode). */
+#define FL_ARCH8 (1 << 24) /* Architecture 8. */
+#define FL_CRC32 (1 << 25) /* ARMv8 CRC32 instructions. */
+
+#define FL_SMALLMUL (1 << 26) /* Small multiply supported. */
+
+#define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
+#define FL_IWMMXT2 (1 << 30) /* "Intel Wireless MMX2 technology". */
+
+/* Flags that only effect tuning, not available instructions. */
+#define FL_TUNE (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \
+ | FL_CO_PROC)
+
+#define FL_FOR_ARCH2 FL_NOTM
+#define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32)
+#define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
+#define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
+#define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
+#define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
+#define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
+#define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
+#define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
+#define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
+#define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
+#define FL_FOR_ARCH6J FL_FOR_ARCH6
+#define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
+#define FL_FOR_ARCH6Z FL_FOR_ARCH6
+#define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
+#define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2)
+#define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM)
+#define FL_FOR_ARCH7 ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7)
+#define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
+#define FL_FOR_ARCH7VE (FL_FOR_ARCH7A | FL_THUMB_DIV | FL_ARM_DIV)
+#define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_THUMB_DIV)
+#define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_THUMB_DIV)
+#define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM)
+#define FL_FOR_ARCH8A (FL_FOR_ARCH7VE | FL_ARCH8)
+
+/* The bits in this mask specify which
+ instructions we are allowed to generate. */
+extern unsigned long insn_flags;
+
+/* The bits in this mask specify which instruction scheduling options should
+ be used. */
+extern unsigned long tune_flags;
+
+/* Nonzero if this chip supports the ARM Architecture 3M extensions. */
+extern int arm_arch3m;
+
+/* Nonzero if this chip supports the ARM Architecture 4 extensions. */
+extern int arm_arch4;
+
+/* Nonzero if this chip supports the ARM Architecture 4t extensions. */
+extern int arm_arch4t;
+
+/* Nonzero if this chip supports the ARM Architecture 5 extensions. */
+extern int arm_arch5;
+
+/* Nonzero if this chip supports the ARM Architecture 5E extensions. */
+extern int arm_arch5e;
+
+/* Nonzero if this chip supports the ARM Architecture 6 extensions. */
+extern int arm_arch6;
+
+/* Nonzero if this chip supports the ARM 6K extensions. */
+extern int arm_arch6k;
+
+/* Nonzero if instructions present in ARMv6-M can be used. */
+extern int arm_arch6m;
+
+/* Nonzero if this chip supports the ARM 7 extensions. */
+extern int arm_arch7;
+
+/* Nonzero if instructions not present in the 'M' profile can be used. */
+extern int arm_arch_notm;
+
+/* Nonzero if instructions present in ARMv7E-M can be used. */
+extern int arm_arch7em;
+
+/* Nonzero if instructions present in ARMv8 can be used. */
+extern int arm_arch8;
+
+/* Nonzero if this chip can benefit from load scheduling. */
+extern int arm_ld_sched;
+
+/* Nonzero if this chip is a StrongARM. */
+extern int arm_tune_strongarm;
+
+/* Nonzero if this chip supports Intel Wireless MMX technology. */
+extern int arm_arch_iwmmxt;
+
+/* Nonzero if this chip supports Intel Wireless MMX2 technology. */
+extern int arm_arch_iwmmxt2;
+
+/* Nonzero if this chip is an XScale. */
+extern int arm_arch_xscale;
+
+/* Nonzero if tuning for XScale */
+extern int arm_tune_xscale;
+
+/* Nonzero if we want to tune for stores that access the write-buffer.
+ This typically means an ARM6 or ARM7 with MMU or MPU. */
+extern int arm_tune_wbuf;
+
+/* Nonzero if tuning for Cortex-A9. */
+extern int arm_tune_cortex_a9;
+
+/* Nonzero if generating Thumb instructions. */
+extern int thumb_code;
+
+/* Nonzero if generating Thumb-1 instructions. */
+extern int thumb1_code;
+
+/* Nonzero if we should define __THUMB_INTERWORK__ in the
+ preprocessor.
+ XXX This is a bit of a hack, it's intended to help work around
+ problems in GLD which doesn't understand that armv5t code is
+ interworking clean. */
+extern int arm_cpp_interwork;
+
+/* Nonzero if chip supports Thumb 2. */
+extern int arm_arch_thumb2;
+
+/* Nonzero if chip supports integer division instruction. */
+extern int arm_arch_arm_hwdiv;
+extern int arm_arch_thumb_hwdiv;
+
+/* Nonzero if we should use Neon to handle 64-bits operations rather
+ than core registers. */
+extern int prefer_neon_for_64bits;
+
+
+
#endif /* ! GCC_ARM_PROTOS_H */
rtx thumb_call_via_label[14];
static int thumb_call_reg_needed;
-/* Bit values used to identify processor capabilities. */
-#define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
-#define FL_ARCH3M (1 << 1) /* Extended multiply */
-#define FL_MODE26 (1 << 2) /* 26-bit mode support */
-#define FL_MODE32 (1 << 3) /* 32-bit mode support */
-#define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
-#define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
-#define FL_THUMB (1 << 6) /* Thumb aware */
-#define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
-#define FL_STRONG (1 << 8) /* StrongARM */
-#define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
-#define FL_XSCALE (1 << 10) /* XScale */
-/* spare (1 << 11) */
-#define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
- media instructions. */
-#define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
-#define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
- Note: ARM6 & 7 derivatives only. */
-#define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */
-#define FL_THUMB2 (1 << 16) /* Thumb-2. */
-#define FL_NOTM (1 << 17) /* Instructions not present in the 'M'
- profile. */
-#define FL_THUMB_DIV (1 << 18) /* Hardware divide (Thumb mode). */
-#define FL_VFPV3 (1 << 19) /* Vector Floating Point V3. */
-#define FL_NEON (1 << 20) /* Neon instructions. */
-#define FL_ARCH7EM (1 << 21) /* Instructions present in the ARMv7E-M
- architecture. */
-#define FL_ARCH7 (1 << 22) /* Architecture 7. */
-#define FL_ARM_DIV (1 << 23) /* Hardware divide (ARM mode). */
-#define FL_ARCH8 (1 << 24) /* Architecture 8. */
-#define FL_CRC32 (1 << 25) /* ARMv8 CRC32 instructions. */
-
-#define FL_SMALLMUL (1 << 26) /* Small multiply supported. */
-
-#define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
-#define FL_IWMMXT2 (1 << 30) /* "Intel Wireless MMX2 technology". */
-
-/* Flags that only effect tuning, not available instructions. */
-#define FL_TUNE (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \
- | FL_CO_PROC)
-
-#define FL_FOR_ARCH2 FL_NOTM
-#define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32)
-#define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
-#define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
-#define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
-#define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
-#define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
-#define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
-#define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
-#define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
-#define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
-#define FL_FOR_ARCH6J FL_FOR_ARCH6
-#define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
-#define FL_FOR_ARCH6Z FL_FOR_ARCH6
-#define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
-#define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2)
-#define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM)
-#define FL_FOR_ARCH7 ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7)
-#define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
-#define FL_FOR_ARCH7VE (FL_FOR_ARCH7A | FL_THUMB_DIV | FL_ARM_DIV)
-#define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_THUMB_DIV)
-#define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_THUMB_DIV)
-#define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM)
-#define FL_FOR_ARCH8A (FL_FOR_ARCH7VE | FL_ARCH8)
-
/* The bits in this mask specify which
instructions we are allowed to generate. */
-static unsigned long insn_flags = 0;
+unsigned long insn_flags = 0;
/* The bits in this mask specify which instruction scheduling options should
be used. */
-static unsigned long tune_flags = 0;
+unsigned long tune_flags = 0;
/* The highest ARM architecture version supported by the
target. */
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