Fix in sincos testbench gen

diff --git a/tests/simple/sincos.v b/tests/simple/sincos.v
index 66156b68508b3a4a8ab825b8e63a3c1ecd92b6cd..b3124337daeee8d2f9ed541afc7f2b73d75c1ce2 100644 (file)
--- a/tests/simple/sincos.v
+++ b/tests/simple/sincos.v
@@ -39,7 +39,7 @@ input start;
 input clock;
 input reset;
 
-(* gentb_constant="0" *)
+(* gentb_constant = 1'b0 *)
 wire reset;
 
 always @(posedge clock, posedge reset) begin: DESIGN_PROCESSOR