getDTBPtr(tc)->flushAllSecurity(secure_lookup, target_el);
return;
// TLBI based on VA, EL0&1 inner sharable (ignored)
- case MISCREG_TLBIMVAIS:
+ case MISCREG_TLBIMVAL:
+ case MISCREG_TLBIMVALIS:
+ // mcr tlbimval(is) is invalidating all matching entries
+ // regardless of the level of lookup, since in gem5 we cache
+ // in the tlb the last level of lookup only.
case MISCREG_TLBIMVA:
+ case MISCREG_TLBIMVAIS:
assert32(tc);
target_el = 1; // el 0 and 1 are handled together
scr = readMiscReg(MISCREG_SCR, tc);
}
return;
// TLBI by address, EL0&1, inner sharable (ignored)
- case MISCREG_TLBIMVAAIS:
+ case MISCREG_TLBIMVAAL:
+ case MISCREG_TLBIMVAALIS:
+ // mcr tlbimvaal(is) is invalidating all matching entries
+ // regardless of the level of lookup, since in gem5 we cache
+ // in the tlb the last level of lookup only.
case MISCREG_TLBIMVAA:
+ case MISCREG_TLBIMVAAIS:
assert32(tc);
target_el = 1; // el 0 and 1 are handled together
scr = readMiscReg(MISCREG_SCR, tc);
tlbiMVA(tc, newVal, secure_lookup, hyp, target_el);
return;
// TLBI by address, EL2, hypervisor mode
+ case MISCREG_TLBIMVALH:
+ case MISCREG_TLBIMVALHIS:
+ // mcr tlbimvalh(is) is invalidating all matching entries
+ // regardless of the level of lookup, since in gem5 we cache
+ // in the tlb the last level of lookup only.
case MISCREG_TLBIMVAH:
case MISCREG_TLBIMVAHIS:
assert32(tc);
return MISCREG_TLBIASIDIS;
case 3:
return MISCREG_TLBIMVAAIS;
+ case 5:
+ return MISCREG_TLBIMVALIS;
+ case 7:
+ return MISCREG_TLBIMVAALIS;
}
break;
case 5:
return MISCREG_TLBIASID;
case 3:
return MISCREG_TLBIMVAA;
+ case 5:
+ return MISCREG_TLBIMVAL;
+ case 7:
+ return MISCREG_TLBIMVAAL;
}
break;
}
return MISCREG_TLBIMVAHIS;
case 4:
return MISCREG_TLBIALLNSNHIS;
+ case 5:
+ return MISCREG_TLBIMVALHIS;
}
} else if (crm == 7) {
switch (opc2) {
return MISCREG_TLBIMVAH;
case 4:
return MISCREG_TLBIALLNSNH;
+ case 5:
+ return MISCREG_TLBIMVALH;
}
}
}
InitReg(MISCREG_TLBIMVAAIS)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBIMVALIS)
- .unimplemented()
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBIMVAALIS)
- .unimplemented()
.writes(1).exceptUserMode();
InitReg(MISCREG_ITLBIALL)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBIMVAA)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBIMVAL)
- .unimplemented()
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBIMVAAL)
- .unimplemented()
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBIIPAS2IS)
.unimplemented()
InitReg(MISCREG_TLBIALLNSNHIS)
.monNonSecureWrite().hypWrite();
InitReg(MISCREG_TLBIMVALHIS)
- .unimplemented()
.monNonSecureWrite().hypWrite();
InitReg(MISCREG_TLBIIPAS2)
.unimplemented()
InitReg(MISCREG_TLBIALLNSNH)
.monNonSecureWrite().hypWrite();
InitReg(MISCREG_TLBIMVALH)
- .unimplemented()
.monNonSecureWrite().hypWrite();
InitReg(MISCREG_PMCR)
.allPrivileges();
case MISCREG_TLBIMVAIS:
case MISCREG_TLBIASIDIS:
case MISCREG_TLBIMVAAIS:
+ case MISCREG_TLBIMVALIS:
+ case MISCREG_TLBIMVAALIS:
case MISCREG_DTLBIALL:
case MISCREG_ITLBIALL:
case MISCREG_DTLBIMVA:
case MISCREG_TLBIMVAA:
case MISCREG_TLBIALL:
case MISCREG_TLBIMVA:
+ case MISCREG_TLBIMVAL:
+ case MISCREG_TLBIMVAAL:
case MISCREG_TLBIASID:
trapToHype = hcr.ttlb;
break;