2005-08-30 Paul Brook <paul@codesourcery.com>

opcodes/
	* arm-dis.c (thumb_opcodes): Disassemble sub(3) as subs.
gas/testsuite/
	* gas/arm/thumb.d: Change "sub rn, rn, rn" to "subs rn, rn, rn".
	* gas/arm/thumb32.d: Ditto.

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 2bddc360f5ffce533e4fc1ce2de9ec2fd29e907d..8769953e51340bea488b22d505b0f4c97d7442f4 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2005-08-30  Paul Brook  <paul@codesourcery.com>
+
+       * gas/arm/thumb.d: Change "sub rn, rn, rn" to "subs rn, rn, rn".
+       * gas/arm/thumb32.d: Ditto.
+
 2005-08-26  Jan Beulich  <jbeulich@novell.com>
 
        * gas/i386/intel.s: Adjust.

diff --git a/gas/testsuite/gas/arm/thumb.d b/gas/testsuite/gas/arm/thumb.d
index 0002a7cdf053a7be7c94f2a0d4b4735b2bf1fba9..53ea6cc11f5a106b0115736bbf00b73a6bd67610 100644 (file)
--- a/gas/testsuite/gas/arm/thumb.d
+++ b/gas/testsuite/gas/arm/thumb.d
@@ -17,8 +17,8 @@ Disassembly of section \.text:
 0+00e <[^>]+> 1008             asrs    r0, r1, #32
 0+010 <[^>]+> 18d1             adds    r1, r2, r3
 0+012 <[^>]+> 1ca2             adds    r2, r4, #2
-0+014 <[^>]+> 1beb             sub     r3, r5, r7
-0+016 <[^>]+> 1fe2             sub     r2, r4, #7
+0+014 <[^>]+> 1beb             subs    r3, r5, r7
+0+016 <[^>]+> 1fe2             subs    r2, r4, #7
 0+018 <[^>]+> 24ff             movs    r4, #255
 0+01a <[^>]+> 2bfa             cmp     r3, #250
 0+01c <[^>]+> 367b             adds    r6, #123

diff --git a/gas/testsuite/gas/arm/thumb32.d b/gas/testsuite/gas/arm/thumb32.d
index 707f2da2c8df0009789c6e6631b1bf830311e68b..2fa28c85bc50fea54aba144375fb8220e44f411d 100644 (file)
--- a/gas/testsuite/gas/arm/thumb32.d
+++ b/gas/testsuite/gas/arm/thumb32.d
@@ -95,10 +95,10 @@ Disassembly of section .text:
 0+13e <[^>]+> f1b0 0005        subs\.w r0, r0, #5      ; 0x5
 0+142 <[^>]+> f1b0 0081        subs\.w r0, r0, #129    ; 0x81
 0+146 <[^>]+> f1b0 0508        subs\.w r5, r0, #8      ; 0x8
-0+14a <[^>]+> 1a00             sub     r0, r0, r0
-0+14c <[^>]+> 1a05             sub     r5, r0, r0
-0+14e <[^>]+> 1a28             sub     r0, r5, r0
-0+150 <[^>]+> 1b40             sub     r0, r0, r5
+0+14a <[^>]+> 1a00             subs    r0, r0, r0
+0+14c <[^>]+> 1a05             subs    r5, r0, r0
+0+14e <[^>]+> 1a28             subs    r0, r5, r0
+0+150 <[^>]+> 1b40             subs    r0, r0, r5
 0+152 <[^>]+> f5a0 7d82        sub\.w  sp, r0, #260    ; 0x104
 0+156 <[^>]+> f5ad 7d82        sub\.w  sp, sp, #260    ; 0x104
 0+15a <[^>]+> ebb8 0800        subs\.w r8, r8, r0

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 4b09b7ae7bad36be1fea1f440be10006c0521664..1d8ed0259a8a6248ee416e42895edb8ce502b029 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2005-08-30  Paul Brook  <paul@codesourcery.com>
+
+       * arm-dis.c (thumb_opcodes): Disassemble sub(3) as subs.
+
 2005-08-26  Jan Beulich  <jbeulich@novell.com>
 
        * i386-dis.c (intel_operand_size): New, broken out from OP_E for

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index dbf91be9e08769541a1784ab19aecbfd249b0876..0f055015373bbd850ef7d3fa55bbb97c6f3c42d2 100644 (file)
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -724,9 +724,9 @@ static const struct opcode16 thumb_opcodes[] =
   {ARM_EXT_V4T, 0xBC00, 0xFE00, "pop\t%O"},
   /* format 2 */
   {ARM_EXT_V4T, 0x1800, 0xFE00, "adds\t%0-2r, %3-5r, %6-8r"},
-  {ARM_EXT_V4T, 0x1A00, 0xFE00, "sub\t%0-2r, %3-5r, %6-8r"},
+  {ARM_EXT_V4T, 0x1A00, 0xFE00, "subs\t%0-2r, %3-5r, %6-8r"},
   {ARM_EXT_V4T, 0x1C00, 0xFE00, "adds\t%0-2r, %3-5r, #%6-8d"},
-  {ARM_EXT_V4T, 0x1E00, 0xFE00, "sub\t%0-2r, %3-5r, #%6-8d"},
+  {ARM_EXT_V4T, 0x1E00, 0xFE00, "subs\t%0-2r, %3-5r, #%6-8d"},
   /* format 8 */
   {ARM_EXT_V4T, 0x5200, 0xFE00, "strh\t%0-2r, [%3-5r, %6-8r]"},
   {ARM_EXT_V4T, 0x5A00, 0xFE00, "ldrh\t%0-2r, [%3-5r, %6-8r]"},