X86: Add wrval/rdval microops for reading significant miscregs.

diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa
index 81aa1dafe5e8c12a124f1ccfb72c60716e49cd9e..f9e0a2fa8b724db7c46d9520dc0e99933845808c 100644 (file)
--- a/src/arch/x86/isa/microasm.isa
+++ b/src/arch/x86/isa/microasm.isa
@@ -159,6 +159,11 @@ let {{
     assembler.symbols["CTrue"] = "ConditionTests::True"
     assembler.symbols["CFalse"] = "ConditionTests::False"
 
+    for reg in ('sysenter_cs', 'sysenter_esp', 'sysenter_eip',
+                'star', 'lstar', 'cstar', 'sf_mask',
+                'kernel_gs_base'):
+        assembler.symbols[reg] = "MISCREG_%s" % reg.upper()
+
     # Code literal which forces a default 64 bit operand size in 64 bit mode.
     assembler.symbols["oszIn64Override"] = '''
     if (machInst.mode.submode == SixtyFourBitMode &&

diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 439116145ee5b3f8e06459389b60143e935c20dc..944d5e9ec61f2a4c17f4d67fde0287fd6b78d03d 100644 (file)
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -1028,6 +1028,22 @@ let {{
             DestReg = SegSelSrc1;
         '''
 
+    class Rdval(RegOp):
+        def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
+            super(Rdval, self).__init__(dest, \
+                    src1, "NUM_INTREGS", flags, dataSize)
+        code = '''
+            DestReg = MiscRegSrc1;
+        '''
+
+    class Wrval(RegOp):
+        def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
+            super(Wrval, self).__init__(dest, \
+                    src1, "NUM_INTREGS", flags, dataSize)
+        code = '''
+            MiscRegDest = SrcReg1;
+        '''
+
     class Chks(RegOp):
         def __init__(self, dest, src1, src2=0,
                 flags=None, dataSize="env.dataSize"):

diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 8bb7c5bb1731d70f3f4146c9fdb33cab98d79517..343b37d413a02a5aff3cca2c78c29499a32ab6dc 100644 (file)
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -153,7 +153,9 @@ def operands {{
         'GDTRLimit':     ('ControlReg', 'uqw', 'MISCREG_TSG_LIMIT', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 206),
         'CSBase':        ('ControlReg', 'udw', 'MISCREG_CS_EFF_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 207),
         'CSAttr':        ('ControlReg', 'udw', 'MISCREG_CS_ATTR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 208),
-        'TscOp':         ('ControlReg', 'udw', 'MISCREG_TSC', (None, None, ['IsSerializeAfter', 'IsSerializing', 'IsNonSpeculative']), 209),
-        'M5Reg':         ('ControlReg', 'udw', 'MISCREG_M5_REG', (None, None, None), 210),
+        'MiscRegDest':   ('ControlReg', 'uqw', 'dest', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 209),
+        'MiscRegSrc1':   ('ControlReg', 'uqw', 'src1', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 210),
+        'TscOp':         ('ControlReg', 'udw', 'MISCREG_TSC', (None, None, ['IsSerializeAfter', 'IsSerializing', 'IsNonSpeculative']), 211),
+        'M5Reg':         ('ControlReg', 'udw', 'MISCREG_M5_REG', (None, None, None), 212),
         'Mem':           ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 300)
 }};