abc -> abc9

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 6c598acf205fc0b6e238de0c65b32fd6f83408d6..07f3d9a8ac1e6a1adcf07ee706828647054d300b 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -481,13 +481,13 @@ struct SynthXilinxPass : public ScriptPass
                                                        "will use timing for 'xc7' instead.\n", family.c_str());
                                run("techmap -map +/xilinx/abc9_map.v -max_iter 1");
                                run("read_verilog -icells -lib +/xilinx/abc9_model.v");
-                               std::string abc9_opts = " -box +/xilinx/abc_xc7.box";
+                               std::string abc9_opts = " -box +/xilinx/abc9_xc7.box";
                                abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY);
                                abc9_opts += " -nomfs";
                                if (nowidelut)
-                                       abc9_opts += " -lut +/xilinx/abc_xc7_nowide.lut";
+                                       abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut";
                                else
-                                       abc9_opts += " -lut +/xilinx/abc_xc7.lut";
+                                       abc9_opts += " -lut +/xilinx/abc9_xc7.lut";
                                run("abc9" + abc9_opts);
                        }
                        else {