sim: h8300: fix test mach markers

These tests all fail to assemble when targeting the h8300 or h8300h
cpu variants with errors like:
rotl.s:242: Warning: Opcode `rotl.b' with these operand types not available in H8/300H mode
rotl.s:242: Error: invalid operands

It's been this way for years and no one seems to care, so disable
them for those targets since the assembler thinks it's impossible.

diff --git a/sim/testsuite/sim/h8300/ChangeLog b/sim/testsuite/sim/h8300/ChangeLog
index a4e7532352b1d927f13c5f6d2e9be5730a08afe0..82128cc43ad51f437d73fc9bcead011170b6cfc4 100644 (file)
--- a/sim/testsuite/sim/h8300/ChangeLog
+++ b/sim/testsuite/sim/h8300/ChangeLog
@@ -1,3 +1,9 @@
+2021-01-05  Mike Frysinger  <vapier@gentoo.org>
+
+       * rotl.s (mach): Set to "h8300s h8sx".
+       * rotr.s, rotxl.s, rotxr.s, shal.s, shar.s, shll.s, shlr.s, tas.s:
+       Likewise.
+
 2021-01-05  Mike Frysinger  <vapier@gentoo.org>
 
        * allinsn.exp: Rewrite file to use globs.

diff --git a/sim/testsuite/sim/h8300/rotl.s b/sim/testsuite/sim/h8300/rotl.s
index 088345d3df7a23b49b5c066f9d8a81a61304cadb..1978c2d557252d2c037e1a3767ab5a555a2e0195 100644 (file)
--- a/sim/testsuite/sim/h8300/rotl.s
+++ b/sim/testsuite/sim/h8300/rotl.s
@@ -1,5 +1,5 @@
 # Hitachi H8 testcase 'rotl'
-# mach(): all
+# mach(): h8300s h8sx
 # as(h8300):   --defsym sim_cpu=0
 # as(h8300h):  --defsym sim_cpu=1
 # as(h8300s):  --defsym sim_cpu=2

diff --git a/sim/testsuite/sim/h8300/rotr.s b/sim/testsuite/sim/h8300/rotr.s
index 2a964c1c29b535d22db26a5108229db54ccf2fc9..658ef821f0ebff3e531dcb6e3a2acc842d128178 100644 (file)
--- a/sim/testsuite/sim/h8300/rotr.s
+++ b/sim/testsuite/sim/h8300/rotr.s
@@ -1,5 +1,5 @@
 # Hitachi H8 testcase 'rotr'
-# mach(): all
+# mach(): h8300s h8sx
 # as(h8300):   --defsym sim_cpu=0
 # as(h8300h):  --defsym sim_cpu=1
 # as(h8300s):  --defsym sim_cpu=2

diff --git a/sim/testsuite/sim/h8300/rotxl.s b/sim/testsuite/sim/h8300/rotxl.s
index 3ae703ef800aa48fd2d9a0cbdfa1219e814897d0..d0ff4a3fb79d60488b93d516c085a430f44162b5 100644 (file)
--- a/sim/testsuite/sim/h8300/rotxl.s
+++ b/sim/testsuite/sim/h8300/rotxl.s
@@ -1,5 +1,5 @@
 # Hitachi H8 testcase 'rotxl'
-# mach(): all
+# mach(): h8300s h8sx
 # as(h8300):   --defsym sim_cpu=0
 # as(h8300h):  --defsym sim_cpu=1
 # as(h8300s):  --defsym sim_cpu=2

diff --git a/sim/testsuite/sim/h8300/rotxr.s b/sim/testsuite/sim/h8300/rotxr.s
index 96ec8a12b6a0bc19f23e1ad0f7e3ac2fe09bcbec..31a351fb23fa9cafe193022ece8f079b7f61615b 100644 (file)
--- a/sim/testsuite/sim/h8300/rotxr.s
+++ b/sim/testsuite/sim/h8300/rotxr.s
@@ -1,5 +1,5 @@
 # Hitachi H8 testcase 'rotxr'
-# mach(): all
+# mach(): h8300s h8sx
 # as(h8300):   --defsym sim_cpu=0
 # as(h8300h):  --defsym sim_cpu=1
 # as(h8300s):  --defsym sim_cpu=2

diff --git a/sim/testsuite/sim/h8300/shal.s b/sim/testsuite/sim/h8300/shal.s
index ccea9071a8bc5292a6524ab5165a36f2cf28246f..5d930d9da632ad4fd57415bcac4c93729a6a0320 100644 (file)
--- a/sim/testsuite/sim/h8300/shal.s
+++ b/sim/testsuite/sim/h8300/shal.s
@@ -1,5 +1,5 @@
 # Hitachi H8 testcase 'shal'
-# mach(): all
+# mach(): h8300s h8sx
 # as(h8300):   --defsym sim_cpu=0
 # as(h8300h):  --defsym sim_cpu=1
 # as(h8300s):  --defsym sim_cpu=2

diff --git a/sim/testsuite/sim/h8300/shar.s b/sim/testsuite/sim/h8300/shar.s
index 9c9166be31b6db9458a502b41d4fe7ce6c9dac93..6b182aa01ce13f1e21fccb42c34ea088c784acf8 100644 (file)
--- a/sim/testsuite/sim/h8300/shar.s
+++ b/sim/testsuite/sim/h8300/shar.s
@@ -1,5 +1,5 @@
 # Hitachi H8 testcase 'shar'
-# mach(): all
+# mach(): h8300s h8sx
 # as(h8300):   --defsym sim_cpu=0
 # as(h8300h):  --defsym sim_cpu=1
 # as(h8300s):  --defsym sim_cpu=2

diff --git a/sim/testsuite/sim/h8300/shll.s b/sim/testsuite/sim/h8300/shll.s
index 7fbf14d056f1ab4cbf59506c8b794ea713abf086..f21a60b81f26535cf376bf821ebb50d832be1feb 100644 (file)
--- a/sim/testsuite/sim/h8300/shll.s
+++ b/sim/testsuite/sim/h8300/shll.s
@@ -1,5 +1,5 @@
 # Hitachi H8 testcase 'shll'
-# mach(): all
+# mach(): h8300s h8sx
 # as(h8300):   --defsym sim_cpu=0
 # as(h8300h):  --defsym sim_cpu=1
 # as(h8300s):  --defsym sim_cpu=2

diff --git a/sim/testsuite/sim/h8300/shlr.s b/sim/testsuite/sim/h8300/shlr.s
index 42233134b453efa47c40b7bdfe60f7f955ae2685..c9f6a08bc83ee663371a024393792a30c33c0cd8 100644 (file)
--- a/sim/testsuite/sim/h8300/shlr.s
+++ b/sim/testsuite/sim/h8300/shlr.s
@@ -1,5 +1,5 @@
 # Hitachi H8 testcase 'shlr'
-# mach(): all
+# mach(): h8300s h8sx
 # as(h8300):   --defsym sim_cpu=0
 # as(h8300h):  --defsym sim_cpu=1
 # as(h8300s):  --defsym sim_cpu=2

diff --git a/sim/testsuite/sim/h8300/tas.s b/sim/testsuite/sim/h8300/tas.s
index b8aebd80deee4c63cfe5cdd7bc137948d58a3691..60bea9200230ee77b311f603cd1ab9012fda76b9 100644 (file)
--- a/sim/testsuite/sim/h8300/tas.s
+++ b/sim/testsuite/sim/h8300/tas.s
@@ -1,5 +1,5 @@
 # Hitachi H8 testcase 'tas'
-# mach(): h8300h h8300s h8sx
+# mach(): h8300s h8sx
 # as(h8300):   --defsym sim_cpu=0
 # as(h8300h):  --defsym sim_cpu=1
 # as(h8300s):  --defsym sim_cpu=2