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diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index a4e91dae2c3a47f3c10111c87a35e2abdcf70de2..c18dfb27d310621cff9faf59400f7f6c25877778 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -252,7 +252,7 @@ This is a novel concept that allows predication to be applied to a single source
 
 Those patterns (and more) may be applied to:
 
-* mv (the usual way that V\* operations are created)
+* mv (the usual way that V\* ISA operations are created)
 * exts\* sign-extension
 * rwlinm and other RS-RA shift operations (**note**: excluding
   those that take RA as both a src and dest. These are not
@@ -265,10 +265,6 @@ This is a huge list that creates extremely powerful combinations, particularly g
 
 Additional unusual capabilities of Twin Predication include a back-to-back version of VCOMPRESS-VEXPAND which is effectively the ability to do an ordered multiple VINSERT.
 
-## Twin Predication
-
-There are two different encodings: single-predication (typically arithmetic operations i.e. with more than one source register) and twin-predication (one source, one destination).  They require different encodings
-
 # Register Naming
 
 SV Registers are numbered using the notation `SV[F|C]R<N>_<M>` where `<N>` is a decimal integer and `<M>` is a binary integer. Two integers are used to enable future register expansions to add more registers by appending more LSB bits to `<M>`.