Fold loop

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 97fec9376b9b95ff3580b276895e14bd648d3a91..9e5d44470dab19ce64b70c94bdaf3941f3233f11 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -174,6 +174,7 @@ struct XAigerWriter
                                        if (bit != wirebit)
                                                alias_map[bit] = wirebit;
                                        input_bits.insert(wirebit);
+                                       undriven_bits.erase(bit);
                                }
 
                                if (wire->port_output || keep) {
@@ -181,6 +182,8 @@ struct XAigerWriter
                                                if (bit != wirebit)
                                                        alias_map[wirebit] = bit;
                                                output_bits.insert(wirebit);
+                                               if (!wire->port_input)
+                                                       unused_bits.erase(bit);
                                        }
                                        else
                                                log_debug("Skipping PO '%s' driven by 1'bx\n", log_signal(wirebit));
@@ -188,12 +191,6 @@ struct XAigerWriter
                        }
                }
 
-               for (auto bit : input_bits)
-                       undriven_bits.erase(sigmap(bit));
-               for (auto bit : output_bits)
-                       if (!bit.wire->port_input)
-                               unused_bits.erase(bit);
-
                // TODO: Speed up toposort -- ultimately we care about
                //       box ordering, but not individual AIG cells
                dict<SigBit, pool<IdString>> bit_drivers, bit_users;