This patch is imported from reviewboard patch 2551 by Nilay.
This patch moves from a dynamically defined MachineType to a statically
defined one. The need for this patch was felt since a dynamically defined
type prevents us from having types for which no machine definition may
exist.
The following changes have been made:
i. each machine definition now uses a type from the MachineType enumeration
instead of any random identifier. This required changing the grammar and the
*.sm files.
ii. MachineType enumeration defined statically in RubySlicc_Exports.sm.
* * *
normal protocol fixes for nilay's parser machine type fix
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(L0Cache, "MESI Directory L0 Cache")
+machine(MachineType:L0Cache, "MESI Directory L0 Cache")
: Sequencer * sequencer;
CacheMemory * Icache;
CacheMemory * Dcache;
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(L1Cache, "MESI Directory L1 Cache CMP")
+machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP")
: CacheMemory * cache;
int l2_select_num_bits;
Cycles l1_request_latency := 2;
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(L1Cache, "MESI Directory L1 Cache CMP")
+machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP")
: Sequencer * sequencer;
CacheMemory * L1Icache;
CacheMemory * L1Dcache;
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(L2Cache, "MESI Directory L2 Cache CMP")
+machine(MachineType:L2Cache, "MESI Directory L2 Cache CMP")
: CacheMemory * L2cache;
Cycles l2_request_latency := 2;
Cycles l2_response_latency := 2;
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(Directory, "MESI Two Level directory protocol")
+machine(MachineType:Directory, "MESI Two Level directory protocol")
: DirectoryMemory * directory;
Cycles to_mem_ctrl_latency := 1;
Cycles directory_latency := 6;
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(DMA, "DMA Controller")
+machine(MachineType:DMA, "DMA Controller")
: DMASequencer * dma_sequencer;
Cycles request_latency := 6;
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(L1Cache, "MI Example L1 Cache")
+machine(MachineType:L1Cache, "MI Example L1 Cache")
: Sequencer * sequencer;
CacheMemory * cacheMemory;
Cycles cache_response_latency := 12;
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(Directory, "Directory protocol")
+machine(MachineType:Directory, "Directory protocol")
: DirectoryMemory * directory;
Cycles directory_latency := 12;
Cycles to_memory_controller_latency := 1;
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(DMA, "DMA Controller")
+machine(MachineType:DMA, "DMA Controller")
: DMASequencer * dma_sequencer;
Cycles request_latency := 6;
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(L1Cache, "Directory protocol")
+machine(MachineType:L1Cache, "Directory protocol")
: Sequencer * sequencer;
CacheMemory * L1Icache;
CacheMemory * L1Dcache;
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(L2Cache, "Token protocol")
+machine(MachineType:L2Cache, "Token protocol")
: CacheMemory * L2cache;
Cycles response_latency := 2;
Cycles request_latency := 2;
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(Directory, "Directory protocol")
+machine(MachineType:Directory, "Directory protocol")
: DirectoryMemory * directory;
Cycles directory_latency := 6;
Cycles to_memory_controller_latency := 1;
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(DMA, "DMA Controller")
+machine(MachineType:DMA, "DMA Controller")
: DMASequencer * dma_sequencer;
Cycles request_latency := 14;
Cycles response_latency := 14;
*
*/
-machine(L1Cache, "Token protocol")
+machine(MachineType:L1Cache, "Token protocol")
: Sequencer * sequencer;
CacheMemory * L1Icache;
CacheMemory * L1Dcache;
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(L2Cache, "Token protocol")
+machine(MachineType:L2Cache, "Token protocol")
: CacheMemory * L2cache;
int N_tokens;
Cycles l2_request_latency := 5;
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(Directory, "Token protocol")
+machine(MachineType:Directory, "Token protocol")
: DirectoryMemory * directory;
int l2_select_num_bits;
Cycles directory_latency := 5;
*/
-machine(DMA, "DMA Controller")
+machine(MachineType:DMA, "DMA Controller")
: DMASequencer * dma_sequencer;
Cycles request_latency := 6;
* Brad Beckmann
*/
-machine(L1Cache, "AMD Hammer-like protocol")
+machine(MachineType:L1Cache, "AMD Hammer-like protocol")
: Sequencer * sequencer;
CacheMemory * L1Icache;
CacheMemory * L1Dcache;
* Brad Beckmann
*/
-machine(Directory, "AMD Hammer-like protocol")
+machine(MachineType:Directory, "AMD Hammer-like protocol")
: DirectoryMemory * directory;
CacheMemory * probeFilter;
Cycles from_memory_controller_latency := 2;
*/
-machine(DMA, "DMA Controller")
+machine(MachineType:DMA, "DMA Controller")
: DMASequencer * dma_sequencer;
Cycles request_latency := 6;
*/
-machine(L1Cache, "Network_test L1 Cache")
+machine(MachineType:L1Cache, "Network_test L1 Cache")
: Sequencer * sequencer;
Cycles issue_latency := 2;
*/
-machine(Directory, "Network_test Directory")
+machine(MachineType:Directory, "Network_test Directory")
: MessageBuffer * requestToDir, network="From", virtual_network="0",
vnet_type = "request";
MessageBuffer * forwardToDir, network="From", virtual_network="1",
Default, desc="Replace this with access_types passed to the DMA Ruby object";
}
+
+// These are statically defined types of states machines that we can have.
+// If you want to add a new machine type, edit this enum. It is not necessary
+// for a protocol to have state machines defined for the all types here. But
+// you cannot use anything other than the ones defined here. Also, a protocol
+// can have only one state machine for a given type.
+enumeration(MachineType, desc="...", default="MachineType_NULL") {
+ L1Cache, desc="L1 Cache Mach";
+ L2Cache, desc="L2 Cache Mach";
+ L3Cache, desc="L3 Cache Mach";
+ Directory, desc="Directory Mach";
+ DMA, desc="DMA Mach";
+ Collector, desc="Collector Mach";
+ L1Cache_wCC, desc="L1 Cache Mach to track cache-to-cache transfer (used for miss latency profile)";
+ L2Cache_wCC, desc="L2 Cache Mach to track cache-to-cache transfer (used for miss latency profile)";
+ NULL, desc="null mach type";
+}
+
// MessageSizeType
enumeration(MessageSizeType, desc="...") {
Control, desc="Control Message";
return s
def generate(self):
- for decl in self.decls:
- decl.generate()
-
- def findMachines(self):
for decl in self.decls:
decl.findMachines()
+ decl.generate()
from slicc.symbols import StateMachine, Type
class MachineAST(DeclAST):
- def __init__(self, slicc, ident, pairs_ast, config_parameters, decls):
+ def __init__(self, slicc, mtype, pairs_ast, config_parameters, decls):
super(MachineAST, self).__init__(slicc, pairs_ast)
- self.ident = ident
+ self.ident = mtype.value
self.pairs_ast = pairs_ast
self.config_parameters = config_parameters
self.decls = decls
def findMachines(self):
mtype = self.ident
machine_type = self.symtab.find("MachineType", Type)
- pairs = self.pairs_ast.pairs
-
- pairs["Primary"] = True
- if not machine_type.addEnum(mtype, pairs):
+ if not machine_type.checkEnum(mtype):
self.error("Duplicate machine name: %s:%s" % (machine_type, mtype))
-
- # Generate code for all the internal decls
- self.decls.findMachines()
return code
def process(self):
- self.decl_list.findMachines()
self.decl_list.generate()
def writeCodeFiles(self, code_path, includes):
self.symtab.writeHTMLFiles(html_path)
def files(self):
- f = set([
- 'MachineType.cc',
- 'MachineType.hh',
- 'Types.hh' ])
+ f = set(['Types.hh'])
f |= self.decl_list.files()
p[0] = self.parse_file(filename)
def p_decl__machine0(self, p):
- "decl : MACHINE '(' ident ')' ':' obj_decls '{' decls '}'"
+ "decl : MACHINE '(' enumeration ')' ':' obj_decls '{' decls '}'"
p[0] = ast.MachineAST(self, p[3], [], p[7], p[9])
def p_decl__machine1(self, p):
- "decl : MACHINE '(' ident pairs ')' ':' obj_decls '{' decls '}'"
+ "decl : MACHINE '(' enumeration pairs ')' ':' obj_decls '{' decls '}'"
p[0] = ast.MachineAST(self, p[3], p[4], p[7], p[9])
def p_decl__action(self, p):
self.sym_map_vec = [ {} ]
self.machine_components = {}
- pairs = {}
- pairs["enumeration"] = "yes"
- location = Location("init", 0, no_warning=not slicc.verbose)
- MachineType = Type(self, "MachineType", location, pairs)
- self.newSymbol(MachineType)
-
pairs = {}
pairs["primitive"] = "yes"
pairs["external"] = "yes"
def __init__(self, ident, pairs):
super(Enumeration, self).__init__(pairs)
self.ident = ident
+ self.primary = False
class Type(Symbol):
def __init__(self, table, ident, location, pairs, machine=None):
return True
+ ## Used to check if an enum has been already used and therefore
+ ## should not be used again.
+ def checkEnum(self, ident):
+ if ident in self.enums and not self.enums[ident].primary:
+ self.enums[ident].primary = True
+ return True
+ return False
+
def writeCodeFiles(self, path, includes):
if self.isExternal:
# Do nothing
if self.isMachineType:
for enum in self.enums.itervalues():
- if enum.get("Primary"):
+ if enum.primary:
code('#include "mem/protocol/${{enum.ident}}_Controller.hh"')
code('#include "mem/ruby/common/MachineID.hh"')
code(' case ${{self.c_ident}}_NUM:')
for enum in reversed(self.enums.values()):
# Check if there is a defined machine with this type
- if enum.get("Primary"):
+ if enum.primary:
code(' base += ${{enum.ident}}_Controller::getNumControllers();')
else:
code(' base += 0;')
# For each field
for enum in self.enums.itervalues():
code('case ${{self.c_ident}}_${{enum.ident}}:')
- if enum.get("Primary"):
+ if enum.primary:
code('return ${{enum.ident}}_Controller::getNumControllers();')
else:
code('return 0;')
projects / gem5.git / commitdiff