sections

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 99aa7768032c0546d15335081148a7e97522ed8a..aeae7e8ae546aa0892df747ea58ce6a227365214 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -272,7 +272,14 @@ For each of EXT059 and EXT063:
   as of 08Sep2022
 
 \newpage{}
-# Use case: LD/ST-Multi
+# Use cases
+
+In the following examples the programs are fully executable under the
+Libre-SOC Simple-V-augmented Power ISA Simulator.  Reproducible
+(scripted) Installation instructions:
+<https://libre-soc.org/HDL_workflow/devscripts/>
+
+## LD/ST-Multi
 
 Context-switching saving and restoring of registers on the stack often
 requires explicit loop-unrolling to achieve effectively.  In SVP64 it
@@ -287,7 +294,7 @@ runtime-configurable LD/ST-Multi is achievable with 2 instructions.
     sv.ld/sm=EQ *rt,0(ra)
 ```
 
-# Use case: Twin-Predication, re-entrant
+## Twin-Predication, re-entrant
 
 This example demonstrates two key concepts: firstly Twin-Predication
 (separate source predicate mask from destination predicate mask) and
@@ -320,7 +327,7 @@ prohibited either.
 
 <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/test_caller_svp64_predication.py;hb=HEAD>
 
-# Use case: 3D GPU style "Branch Conditional"
+## 3D GPU style "Branch Conditional"
 
 (*Note: Specification is ready, Simulator still under development of
 full specification capabilities*)
@@ -330,7 +337,6 @@ avoids the need for additional instructions that would need to
 perform a Parallel Reduction of a Vector of Condition Register
 tests down to a single value, on which a Scalar Branch-Conditional
 could then be performed.  Full Rationale at
-
 <https://libre-soc.org/openpower/sv/branches/>
 
 ```
@@ -351,7 +357,7 @@ could then be performed.  Full Rationale at
 <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/test_caller_svp64_bc.py;hb=HEAD>
 
 \newpage{}
-# Use case: DCT
+## DCT
 
 DCT has dozens of uses in Audio-Visual processing and CODECs.
 A full 8-wide in-place triple-loop Inverse DCT may be achieved
@@ -378,7 +384,7 @@ The cosine table may be computed (once) with 18 Vector instructions
 
 <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/test_caller_svp64_dct.py;hb=HEAD>
 
-# Use case: Matrix Multiply
+## Matrix Multiply
 
 Matrix Multiply of any size (non-power-2) up to a total of 127 operations
 is achievable with only three instructions.  Normally in any other SIMD
@@ -396,7 +402,7 @@ repetition of data is required.  These 3 instructions may be used as the
 
 <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/test_caller_svp64_matrix.py;hb=HEAD>
 
-# Use case: Parallel Reduction
+## Parallel Reduction
 
 Parallel (Horizontal) Reduction is often deeply problematic in SIMD and
 Vector ISAs.  Parallel Reduction is Fully Deterministic in Simple-V and