Merge branch 'master' into map_cells_before_map_luts

diff --cc techlibs/xilinx/synth_xilinx.cc
index b82ab93373a4bd27f129d90443029be394343310,397c83ac6f8cc489b2b59bd35e327a0f1d8d4d03..da6c0a4b25bd0ff1b5acc4d36236b4b89050739f
--- 1/techlibs/xilinx/synth_xilinx.cc
--- 2/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@@ -110,20 -110,20 +110,20 @@@ struct SynthXilinxPass : public Pas
                log("        dffsr2dff\n");
                log("        dff2dffe\n");
                log("        opt -full\n");
-               log("        techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n");
+               log("        techmap -map +/techmap.v -map +/xilinx/arith_map.v\n");
                log("        opt -fast\n");
                log("\n");
-               log("        dffinit -ff FDRE   Q INIT -ff FDCE   Q INIT -ff FDPE   Q INIT -ff FDSE   Q INIT \\\n");
-               log("                -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n");
 +              log("    map_cells:\n");
 +              log("        techmap -map +/xilinx/cells_map.v\n");
 +              log("        clean\n");
 +              log("\n");
                log("    map_luts:\n");
-               log("        abc -luts 2:2,3,6:5,10,20 [-dff] (without '-vpr' only!)\n");
-               log("        abc -lut 5 [-dff] (with '-vpr' only!)\n");
+               log("        techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?\n");
+               log("        abc -luts 2:2,3,6:5,10,20 [-dff]\n");
                log("        clean\n");
-               log("        techmap -map +/xilinx/lut_map.v\n");
+               log("        techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
 -              log("\n");
 -              log("    map_cells:\n");
 -              log("        techmap -map +/xilinx/cells_map.v\n");
+               log("        dffinit -ff FDRE   Q INIT -ff FDCE   Q INIT -ff FDPE   Q INIT -ff FDSE   Q INIT \\\n");
+               log("                -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n");
 -              log("        clean\n");
                log("\n");
                log("    check:\n");
                log("        hierarchy -check\n");
@@@ -266,19 -266,20 +266,20 @@@
                        Pass::call(design, "opt -fast");
                }
  
-                       Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
-                                       "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
 +              if (check_label(active, run_from, run_to, "map_cells"))
 +              {
 +                      Pass::call(design, "techmap -map +/xilinx/cells_map.v");
 +                      Pass::call(design, "clean");
 +              }
 +
                if (check_label(active, run_from, run_to, "map_luts"))
                {
+                       Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?");
                        Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
                        Pass::call(design, "clean");
-                       Pass::call(design, "techmap -map +/xilinx/lut_map.v");
+                       Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
 -              }
 -
 -              if (check_label(active, run_from, run_to, "map_cells"))
 -              {
 -                      Pass::call(design, "techmap -map +/xilinx/cells_map.v");
+                       Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
+                                       "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
 -                      Pass::call(design, "clean");
                }
  
                if (check_label(active, run_from, run_to, "check"))