pan/midgard: Handle misc. cppcheck warnings

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

diff --git a/src/panfrost/midgard/disassemble.c b/src/panfrost/midgard/disassemble.c
index 784dba9a9c910ee7c416038d18d32dc0050d8443..0b4dc72be9f9b7b475bb51d2ca0f4316c60b5739 100644 (file)
--- a/src/panfrost/midgard/disassemble.c
+++ b/src/panfrost/midgard/disassemble.c
@@ -487,10 +487,8 @@ print_mask(uint8_t mask, unsigned bits, midgard_dest_override override)
 
         const char *alphabet = components;
 
-        if (override == midgard_dest_override_upper) {
-                unsigned components = 128 / bits;
-                alphabet += components;
-        }
+        if (override == midgard_dest_override_upper)
+                alphabet += (128 / bits);
 
         for (unsigned i = 0; i < 8; i += skip) {
                 bool a = (mask & (1 << i)) != 0;
@@ -1310,7 +1308,7 @@ print_texture_word(uint32_t *word, unsigned tabs, unsigned in_reg_base, unsigned
         /* Output modifiers are always interpreted floatly */
         print_outmod(texture->outmod, false);
 
-        printf(" %sr%d", texture->out_full ? "" : "h",
+        printf(" %sr%u", texture->out_full ? "" : "h",
                         out_reg_base + texture->out_reg_select);
         print_mask_4(texture->mask, texture->out_upper);
         assert(!(texture->out_full && texture->out_upper));
@@ -1346,7 +1344,7 @@ print_texture_word(uint32_t *word, unsigned tabs, unsigned in_reg_base, unsigned
         }
 
         print_swizzle_vec4(texture->swizzle, false, false);
-        printf(", %sr%d", texture->in_reg_full ? "" : "h", in_reg_base + texture->in_reg_select);
+        printf(", %sr%u", texture->in_reg_full ? "" : "h", in_reg_base + texture->in_reg_select);
         assert(!(texture->in_reg_full && texture->in_reg_upper));
 
         /* TODO: integrate with swizzle */
@@ -1372,7 +1370,7 @@ print_texture_word(uint32_t *word, unsigned tabs, unsigned in_reg_base, unsigned
                 bool select = texture->offset_x & 2;
                 bool upper = texture->offset_x & 4;
 
-                printf("%sr%d", full ? "" : "h", in_reg_base + select);
+                printf("%sr%u", full ? "" : "h", in_reg_base + select);
                 assert(!(texture->out_full && texture->out_upper));
 
                 /* TODO: integrate with swizzle */

diff --git a/src/panfrost/midgard/midgard_emit.c b/src/panfrost/midgard/midgard_emit.c
index fca181334bb8d2b0d09538d2a6f0166fd009d368..bda01acce8baa5bdc9404b68b50fe65d1782adc2 100644 (file)
--- a/src/panfrost/midgard/midgard_emit.c
+++ b/src/panfrost/midgard/midgard_emit.c
@@ -142,7 +142,7 @@ mir_pack_swizzle_64(unsigned *swizzle, unsigned max_component)
         for (unsigned i = 0; i < 2; ++i) {
                 assert(swizzle[i] <= max_component);
 
-                unsigned a = swizzle[i] & 1 ?
+                unsigned a = (swizzle[i] & 1) ?
                         (COMPONENT_W << 2) | COMPONENT_Z :
                         (COMPONENT_Y << 2) | COMPONENT_X;
 

diff --git a/src/panfrost/midgard/midgard_ra_pipeline.c b/src/panfrost/midgard/midgard_ra_pipeline.c
index a85383fc249c5f17c4d6b526e60fbe166d05dd70..7a8c7b118e217109b1253f77940b1fbe5abc4d30 100644 (file)
--- a/src/panfrost/midgard/midgard_ra_pipeline.c
+++ b/src/panfrost/midgard/midgard_ra_pipeline.c
@@ -56,8 +56,8 @@ mir_pipeline_ins(
 
         /* Analyze the bundle for a per-byte read mask */
 
-        for (unsigned i = 0; i < bundle->instruction_count; ++i) {
-                midgard_instruction *q = bundle->instructions[i];
+        for (unsigned j = 0; j < bundle->instruction_count; ++j) {
+                midgard_instruction *q = bundle->instructions[j];
                 read_mask |= mir_bytemask_of_read_components(q, node);
 
                 /* The fragment colour can't be pipelined (well, it is
@@ -69,8 +69,8 @@ mir_pipeline_ins(
         }
 
         /* Now analyze for a write mask */
-        for (unsigned i = 0; i < bundle->instruction_count; ++i) {
-                midgard_instruction *q = bundle->instructions[i];
+        for (unsigned j = 0; j < bundle->instruction_count; ++j) {
+                midgard_instruction *q = bundle->instructions[j];
                 if (q->dest != node) continue;
 
                 /* Remove the written mask from the read requirements */

diff --git a/src/panfrost/midgard/midgard_schedule.c b/src/panfrost/midgard/midgard_schedule.c
index f2e9a3c8e9c6165003ea20d0e63c1b0bdc59f2b1..6d83330a50224c8f96701b4d39e0f99e1921d258 100644 (file)
--- a/src/panfrost/midgard/midgard_schedule.c
+++ b/src/panfrost/midgard/midgard_schedule.c
@@ -914,12 +914,12 @@ mir_schedule_alu(
         mir_choose_alu(&sadd, instructions, worklist, len, &predicate, UNIT_SADD);
 
         /* Check if writeout reads its own register */
-        bool bad_writeout = false;
 
         if (branch && branch->writeout) {
                 midgard_instruction *stages[] = { sadd, vadd, smul };
                 unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(0) : branch->src[0];
                 unsigned writeout_mask = 0x0;
+                bool bad_writeout = false;
 
                 for (unsigned i = 0; i < ARRAY_SIZE(stages); ++i) {
                         if (!stages[i])

diff --git a/src/panfrost/midgard/mir.c b/src/panfrost/midgard/mir.c
index 3f4d53c578114e8c089bfb9ad9f4d0fc901bfd11..2c0248bf0505f2d6f38d79aff8ee7587e6f1f2e1 100644 (file)
--- a/src/panfrost/midgard/mir.c
+++ b/src/panfrost/midgard/mir.c
@@ -312,7 +312,7 @@ mir_to_bytemask(midgard_reg_mode mode, unsigned mask)
 
         case midgard_reg_mode_16: {
                 unsigned space =
-                        ((mask & 0x1) << (0 - 0)) |
+                        (mask & 0x1) |
                         ((mask & 0x2) << (2 - 1)) |
                         ((mask & 0x4) << (4 - 2)) |
                         ((mask & 0x8) << (6 - 3)) |
@@ -326,7 +326,7 @@ mir_to_bytemask(midgard_reg_mode mode, unsigned mask)
 
         case midgard_reg_mode_32: {
                 unsigned space =
-                        ((mask & 0x1) << (0 - 0)) |
+                        (mask & 0x1) |
                         ((mask & 0x2) << (4 - 1)) |
                         ((mask & 0x4) << (8 - 2)) |
                         ((mask & 0x8) << (12 - 3));