correct link

diff --git a/simple_v_extension/vblock_format.mdwn b/simple_v_extension/vblock_format.mdwn
index 49b005cbe4097167e9c6fdef4ac65c139da6fa16..98fa2bb3451f85f39c326dc0800f40afafebc1db 100644 (file)
--- a/simple_v_extension/vblock_format.mdwn
+++ b/simple_v_extension/vblock_format.mdwn
@@ -29,8 +29,8 @@ Note: The VL Block format is similar to that used in [[sv_prefix_proposal]].
 
 * Mode 0b00: set VL to the immediate, truncated to not exceed
   MVL. Register rd is also set to the same value, if not x0.
-* Mode 0b01: follow [[sv.setvl]] rules except with RVC style registers
-  in the range x8-x15 for rs1 and rd.
+* Mode 0b01: follow [[specification/sv.setvl]] rules, with RVC
+  style registers in the range x8-x15 for rs1 and rd.
 * Mode 0b10: set both MVL and VL to the immediate. Register rd is also
   set if not x0.
 * Mode 0b11: reserved. All fields must be zero.