* cdtbcd RA, RS
+Pseudo-code:
+
do i = 0 to 1
n <- i * 32
RA[n+0:n+7] <- 0
None
# Add and Generate Sixes
+# Add and Generate Sixes
XO-Form
* addg6s RT,RA,RB
+Pseudo-code:
+
do i = 0 to 15
dci <- carry_out(RA[4*i:63] + RB[4*i:63])
c <- ([dc[0]]*4 || [dc[1]]*4 || [dc[2]]*4 || [dc[3]]*4 ||
None
# Convert Binary Coded Decimal To Declets
+# Convert Binary Coded Decimal To Declets
X-Form
* cbcdtd RA, RS
+Pseudo-code:
+
do i = 0 to 1
n <- i * 32
RA[n+0:n+11] <- 0
-# Branch
+# Branch
I-Form
* bl target_addr (AA=0 LK=1)
* bla target_addr (AA=1 LK=1)
+Pseudo-code:
+
if AA then NIA <-iea EXTS(LI || 0b00)
else NIA <-iea CIA + EXTS(LI || 0b00)
if LK then LR <-iea CIA + 4
LR (if LK=1)
# Branch Conditional
+# Branch Conditional
B-Form
* bcl BO,BI,target_addr (AA=0 LK=1)
* bcla BO,BI,target_addr (AA=1 LK=1)
+Pseudo-code:
+
if (mode_is_64bit) then M <- 0
else M <- 32
if ¬BO[2] then CTR <- CTR - 1
LR (if LK=1)
# Branch Conditional to Link Register
+# Branch Conditional to Link Register
XL-Form
* bclr BO,BI,BH (LK=0)
* bclrl BO,BI,BH (LK=1)
+Pseudo-code:
+
if (mode_is_64bit) then M <- 0
else M <- 32
if ¬BO[2] then CTR <- CTR - 1
LR (if LK=1)
# Branch Conditional to Count Register
+# Branch Conditional to Count Register
XL-Form
* bcctr BO,BI,BH (LK=0)
* bcctrl BO,BI,BH (LK=1)
+Pseudo-code:
+
cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
if cond_ok then NIA <-iea CTR[0:61] || 0b00
if LK then LR <-iea CIA + 4
LR (if LK=1)
# Branch Conditional to Branch Target Address Register
+# Branch Conditional to Branch Target Address Register
XL-Form
* bctar BO,BI,BH (LK=0)
* bctarl BO,BI,BH (LK=1)
+Pseudo-code:
+
if (mode_is_64bit) then M <- 0
else M <- 32
if ¬BO[2] then CTR <- CTR - 1
* cmpi BF,L,RA,SI
+Pseudo-code:
+
if L = 0 then a <- EXTS((RA)[32:63])
else a <- (RA)
if a < EXTS(SI) then c <- 0b100
CR field BF
# Compare
+# Compare
X-Form
* cmp BF,L,RA,RB
+Pseudo-code:
+
if L = 0 then
a <- EXTS((RA)[32:63] )
b <- EXTS((RB)[32:63])
CR field BF
# Compare Logical Immediate
+# Compare Logical Immediate
D-Form
* cmpli BF,L,RA,UI
+Pseudo-code:
+
if L = 0 then a <- [0]*32 || (RA)[32:63]
else a <- (RA)
if a <u ( [0]*48 || UI) then c <- 0b100
CR field BF
# Compare Logical
+# Compare Logical
X-Form
* cmpl BF,L,RA,RB
+Pseudo-code:
+
if L = 0 then
a <- [0]*32 || (RA)[32:63]
b <- [0]*32 || (RB)[32:63]
CR field BF
# Compare Ranged Byte
+# Compare Ranged Byte
X-Form
* cmprb BF,L,RA,RB
+Pseudo-code:
+
src1 <- EXTZ((RA)[56:63])
src21hi <- EXTZ((RB)[32:39])
src21lo <- EXTZ((RB)[40:47])
CR field BF
# Compare Equal Byte
+# Compare Equal Byte
X-Form
* cmpeqb BF,RA,RB
+Pseudo-code:
+
src1 <- GPR[RA]
src1 <- src1[56:63]
match <- ((src1 = (RB)[00:07]) |
* crand BT,BA,BB
+Pseudo-code:
+
CR[BT+32] <- CR[BA+32] & CR[BB+32]
Special Registers Altered:
CR[BT+32]
# Condition Register NAND
+# Condition Register NAND
XL-Form
* crnand BT,BA,BB
+Pseudo-code:
+
CR[BT+32] <- ¬(CR[BA+32] & CR[BB+32])
Special Registers Altered:
CR[BT+32]
# Condition Register OR
+# Condition Register OR
XL-Form
* cror BT,BA,BB
+Pseudo-code:
+
CR[BT+32] <- CR[BA+32] | CR[BB+32]
Special Registers Altered:
CR[BT+32]
# Condition Register XOR
+# Condition Register XOR
XL-Form
* crxor BT,BA,BB
+Pseudo-code:
+
CR[BT+32] <- CR[BA+32] ^ CR[BB+32]
Special Registers Altered:
CR[BT+32]
# Condition Register NOR
+# Condition Register NOR
XL-Form
* crnor BT,BA,BB
+Pseudo-code:
+
CR[BT+32] <- ¬(CR[BA+32] | CR[BB+32])
Special Registers Altered:
CR[BT+32]
# Condition Register Equivalent
+# Condition Register Equivalent
XL-Form
* creqv BT,BA,BB
+Pseudo-code:
+
CR[BT+32] <- ¬(CR[BA+32] ^ CR[BB+32])
Special Registers Altered:
CR[BT+32]
-# Condition Register AND with Complement
+# Condition Register AND with Complement
+# Condition Register AND with Complement
XL-Form
* crandc BT,BA,BB
+Pseudo-code:
+
CR[BT+32] <- CR[BA+32] & ¬CR[BB+32]
Special Registers Altered:
CR[BT+32]
# Condition Register OR with Complement
+# Condition Register OR with Complement
XL-Form
* crorc BT,BA,BB
+Pseudo-code:
+
CR[BT+32] <- CR[BA+32] | ¬CR[BB+32]
Special Registers Altered:
CR[BT+32]
# Move Condition Register Field
+# Move Condition Register Field
XL-Form
* mcrf BF,BFA
+Pseudo-code:
+
CR[4*BF+32:4*BF+35] <- CR[4*BFA+32:4*BFA+35]
Special Registers Altered:
* addi RT,RA,SI
+Pseudo-code:
+
if RA = 0 then RT <- EXTS(SI)
else RT <- (RA) + EXTS(SI)
None
# Add Immediate Shifted
+# Add Immediate Shifted
D-Form
* addis RT,RA,SI
+Pseudo-code:
+
if RA = 0 then RT <- EXTS(SI || [0]*16)
else RT <- (RA) + EXTS(SI || [0]*16)
None
# Add PC Immediate Shifted
+# Add PC Immediate Shifted
DX-Form
* addpcis RT,D
+Pseudo-code:
+
D <- d0||d1||d2
RT <- NIA + EXTS(D || [0]*16)
None
# Add
+# Add
XO-Form
* addo RT,RA,RB (OE=1 Rc=0)
* addo. RT,RA,RB (OE=1 Rc=1)
+Pseudo-code:
+
RT <- (RA) + (RB)
Special Registers Altered:
SO OV OV32 (if OE=1)
# Subtract From
+# Subtract From
XO-Form
* subfo RT,RA,RB (OE=1 Rc=0)
* subfo. RT,RA,RB (OE=1 Rc=1)
+Pseudo-code:
+
RT <- ¬(RA) + (RB) + 1
Special Registers Altered:
SO OV OV32 (if OE=1)
# Add Immediate Carrying
+# Add Immediate Carrying
D-Form
* addic RT,RA,SI
+Pseudo-code:
+
RT <- (RA) + EXTS(SI)
Special Registers Altered:
CA CA32
# Add Immediate Carrying and Record
+# Add Immediate Carrying and Record
D-Form
* addic. RT,RA,SI
+Pseudo-code:
+
RT <- (RA) + EXTS(SI)
Special Registers Altered:
CR0 CA CA32
# Subtract From Immediate Carrying
+# Subtract From Immediate Carrying
D-Form
* subfic RT,RA,SI
+Pseudo-code:
+
RT <- ¬(RA) + EXTS(SI) + 1
Special Registers Altered:
CA CA32
# Add Carrying
+# Add Carrying
XO-Form
* addco RT,RA,RB (OE=1 Rc=0)
* addco. RT,RA,RB (OE=1 Rc=1)
+Pseudo-code:
+
RT <- (RA) + (RB)
Special Registers Altered:
SO OV OV32 (if OE=1)
# Subtract From Carrying
+# Subtract From Carrying
XO-Form
* subfco RT,RA,RB (OE=1 Rc=0)
* subfco. RT,RA,RB (OE=1 Rc=1)
+Pseudo-code:
+
RT <- ¬(RA) + (RB) + 1
Special Registers Altered:
SO OV OV32 (if OE=1)
# Add Extended
+# Add Extended
XO-Form
* addeo RT,RA,RB (OE=1 Rc=0)
* addeo. RT,RA,RB (OE=1 Rc=1)
+Pseudo-code:
+
RT <- (RA) + (RB) + CA
Special Registers Altered:
SO OV OV32 (if OE=1)
# Subtract From Extended
+# Subtract From Extended
XO-Form
* subfeo RT,RA,RB (OE=1 Rc=0)
* subfeo. RT,RA,RB (OE=1 Rc=1)
+Pseudo-code:
+
RT <- ¬(RA) + (RB) + CA
Special Registers Altered:
SO OV OV32 (if OE=1)
# Add to Minus One Extended
+# Add to Minus One Extended
XO-Form
* addmeo RT,RA (OE=1 Rc=0)
* addmeo. RT,RA (OE=1 Rc=1)
+Pseudo-code:
+
RT <- (RA) + CA - 1
Special Registers Altered:
SO OV OV32 (if OE=1)
# Subtract From Minus One Extended
+# Subtract From Minus One Extended
XO-Form
* subfmeo RT,RA (OE=1 Rc=0)
* subfmeo. RT,RA (OE=1 Rc=1)
+Pseudo-code:
+
RT <- ¬(RA) + CA - 1
Special Registers Altered:
SO OV OV32 (if OE=1)
# Add Extended using alternate carry bit
+# Add Extended using alternate carry bit
Z23-Form
* addex RT,RA,RB,CY
+Pseudo-code:
+
if CY=0 then RT <- (RA) + (RB) + OV
Special Registers Altered:
OV OV32 (if CY=0 )
# Subtract From Zero Extended
+# Subtract From Zero Extended
XO-Form
* subfzeo RT,RA (OE=1 Rc=0)
* subfzeo. RT,RA (OE=1 Rc=1)
+Pseudo-code:
+
RT <- ¬(RA) + CA
Special Registers Altered:
SO OV OV32 (if OE=1)
# Add to Zero Extended
+# Add to Zero Extended
XO-Form
* addzeo RT,RA (OE=1 Rc=0)
* addzeo. RT,RA (OE=1 Rc=1)
+Pseudo-code:
+
RT <- (RA) + CA
Special Registers Altered:
SO OV OV32 (if OE=1)
# Negate
+# Negate
XO-Form
* nego RT,RA (OE=1 Rc=0)
* nego. RT,RA (OE=1 Rc=1)
+Pseudo-code:
+
RT <- ¬(RA) + 1
Special Registers Altered:
SO OV OV32 (if OE=1)
# Multiply Low Immediate
+# Multiply Low Immediate
D-Form
* mulli RT,RA,SI
+Pseudo-code:
+
prod[0:127] <- (RA) * EXTS(SI)
RT <- prod[64:127]
None
# Multiply High Word
+# Multiply High Word
XO-Form
* mulhw RT,RA,RB (Rc=0)
* mulhw. RT,RA,RB (Rc=1)
+Pseudo-code:
+
prod[0:63] <- (RA)[32:63] * (RB)[32:63]
RT[32:63] <- prod[0:31]
RT[0:31] <- undefined[0:31]
CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
# Multiply Low Word
+# Multiply Low Word
XO-Form
* mullwo RT,RA,RB (OE=1 Rc=0)
* mullwo. RT,RA,RB (OE=1 Rc=1)
+Pseudo-code:
+
RT <- (RA)[32:63] * (RB)[32:63]
Special Registers Altered:
SO OV OV32 (if OE=1)
# Multiply High Word Unsigned
+# Multiply High Word Unsigned
XO-Form
* mulhwu RT,RA,RB (Rc=0)
* mulhwu. RT,RA,RB (Rc=1)
+Pseudo-code:
+
prod[0:63] <- (RA)[32:63] * (RB)[32:63]
RT[32:63] <- prod[0:31]
RT[0:31] <- undefined[0:31]
CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
# Divide Word
+# Divide Word
XO-Form
* divwo RT,RA,RB (OE=1 Rc=0)
* divwo. RT,RA,RB (OE=1 Rc=1)
+Pseudo-code:
+
dividend[0:31] <- (RA)[32:63]
divisor[0:31] <- (RB) [32:63]
if (((dividend = 0x8000_0000) &
SO OV OV32 (if OE=1)
# Divide Word Unsigned
+# Divide Word Unsigned
XO-Form
* divwuo RT,RA,RB (OE=1 Rc=0)
* divwuo. RT,RA,RB (OE=1 Rc=1)
+Pseudo-code:
+
dividend[0:31] <- (RA)[32:63]
divisor[0:31] <- (RB)[32:63]
if divisor != 0 then
SO OV OV32 (if OE=1)
# Divide Word Extended
+# Divide Word Extended
XO-Form
* divweo RT,RA,RB (OE=1 Rc=0)
* divweo. RT,RA,RB (OE=1 Rc=1)
+Pseudo-code:
+
dividend[0:63] <- (RA)[32:63] || [0]*32
divisor[0:63] <- [0]*32 || (RB)[32:63]
if (divisor = 0x0000_0000_0000_0000) then
SO OV OV32 (if OE=1)
# Divide Word Extended Unsigned
+# Divide Word Extended Unsigned
XO-Form
* divweuo RT,RA,RB (OE=1 Rc=0)
* divweuo. RT,RA,RB (OE=1 Rc=1)
+Pseudo-code:
+
dividend[0:63] <- (RA)[32:63] || [0]*32
divisor[0:63] <- [0]*32 || (RB)[32:63]
if (divisor = 0x0000_0000_0000_0000) then
SO OV OV32 (if OE=1)
# Modulo Signed Word
+# Modulo Signed Word
X-Form
* modsw RT,RA,RB
+Pseudo-code:
+
dividend[0:31] <- (RA)[32:63]
divisor [0:31] <- (RB)[32:63]
if (((dividend = 0x8000_0000) &
None
# Modulo Unsigned Word
+# Modulo Unsigned Word
X-Form
* moduw RT,RA,RB
+Pseudo-code:
+
dividend[0:31] <- (RA) [32:63]
divisor [0:31] <- (RB) [32:63]
if divisor = 0x0000_0000 then
None
# Deliver A Random Number
+# Deliver A Random Number
X-Form
* darn RT,L
+Pseudo-code:
+
RT <- random(L)
Special Registers Altered:
none
# Multiply Low Doubleword
+# Multiply Low Doubleword
XO-Form
* mulldo RT,RA,RB (OE=1 Rc=0)
* mulldo. RT,RA,RB (OE=1 Rc=1)
+Pseudo-code:
+
prod[0:127] <- (RA) * (RB)
RT <- prod[64:127]
SO OV OV32 (if OE=1)
# Multiply High Doubleword
+# Multiply High Doubleword
XO-Form
* mulhd RT,RA,RB (Rc=0)
* mulhd. RT,RA,RB (Rc=1)
+Pseudo-code:
+
prod[0:127] <- (RA) * (RB)
RT <- prod[0:63]
CR0 (if Rc=1)
# Multiply High Doubleword Unsigned
+# Multiply High Doubleword Unsigned
XO-Form
* mulhdu RT,RA,RB (Rc=0)
* mulhdu. RT,RA,RB (Rc=1)
+Pseudo-code:
+
prod[0:127] <- (RA) * (RB)
RT <- prod[0:63]
CR0 (if Rc=1)
# Multiply-Add High Doubleword VA-Form
+# Multiply-Add High Doubleword VA-Form
VA-Form
* maddhd RT,RA.RB,RC
+Pseudo-code:
+
prod[0:127] <- (RA) * (RB)
sum[0:127] <- prod + EXTS(RC)
RT <- sum[0:63]
None
# Multiply-Add High Doubleword Unsigned
+# Multiply-Add High Doubleword Unsigned
VA-Form
* maddhdu RT,RA.RB,RC
+Pseudo-code:
+
prod[0:127] <- (RA) * (RB)
sum[0:127] <- prod + EXTZ(RC)
RT <- sum[0:63]
None
# Multiply-Add Low Doubleword
+# Multiply-Add Low Doubleword
VA-Form
* maddld RT,RA.RB,RC
+Pseudo-code:
+
prod[0:127] <- (RA) * (RB)
sum[0:127] <- prod + EXTS(RC)
RT <- sum[64:127]
None
# Divide Doubleword
+# Divide Doubleword
XO-Form
* divdo RT,RA,RB (OE=1 Rc=0)
* divdo. RT,RA,RB (OE=1 Rc=1)
+Pseudo-code:
+
dividend[0:63] <- (RA)
divisor[0:63] <- (RB)
if (((dividend = 0x8000_0000_0000_0000) &
SO OV OV32 (if OE=1)
# Divide Doubleword Unsigned
+# Divide Doubleword Unsigned
XO-Form
* divduo RT,RA,RB (OE=1 Rc=0)
* divduo. RT,RA,RB (OE=1 Rc=1)
+Pseudo-code:
+
dividend[0:63] <- (RA)
divisor[0:63] <- (RB)
if (divisor = 0x0000_0000_0000_0000) then
SO OV OV32 (if OE=1)
# Divide Doubleword Extended
+# Divide Doubleword Extended
XO-Form
* divdeo RT,RA,RB (OE=1 Rc=0)
* divdeo. RT,RA,RB (OE=1 Rc=1)
+Pseudo-code:
+
dividend[0:127] <- (RA) || [0]*64
divisor[0:127] <- [0*64] || (RB)
if divisor = [0]*128 then
SO OV OV32 (if OE=1)
# Divide Doubleword Extended Unsigned
+# Divide Doubleword Extended Unsigned
XO-Form
* divdeuo RT,RA,RB (OE=1 Rc=0)
* divdeuo. RT,RA,RB (OE=1 Rc=1)
+Pseudo-code:
+
dividend[0:127] <- (RA) || [0]*64
divisor[0:127] <- [0*64] || (RB)
if divisor = [0]*128 then
SO OV OV32 (if OE=1)
# Modulo Signed Doubleword
+# Modulo Signed Doubleword
X-Form
* modsd RT,RA,RB
+Pseudo-code:
+
dividend <- (RA)
divisor <- (RB)
if (((dividend = 0x8000_0000_0000_0000) &
None
# Modulo Unsigned Doubleword
+# Modulo Unsigned Doubleword
X-Form
* modud RT,RA,RB
+Pseudo-code:
+
dividend <- (RA)
divisor <- (RB)
if (divisor = 0x0000_0000_0000_0000) then
* lbz RT,D(RA)
+Pseudo-code:
+
b <- (RA|0)
EA <- b + EXTS(D)
RT <- [0]*56 || MEM(EA, 1)
None
# Load Byte and Zero Indexed
+# Load Byte and Zero Indexed
X-Form
* lbzx RT,RA,RB
+Pseudo-code:
+
b <- (RA|0)
EA <- b + (RB)
RT <- [0] * 56 || MEM(EA, 1)
None
# Load Byte and Zero with Update
+# Load Byte and Zero with Update
D-Form
* lbzu RT,D(RA)
+Pseudo-code:
+
EA <- (RA) + EXTS(D)
RT <- [0] * 56 || MEM(EA, 1)
RA <- EA
None
# Load Byte and Zero with Update Indexed
+# Load Byte and Zero with Update Indexed
X-Form
* lbzux RT,RA,RB
+Pseudo-code:
+
EA <- (RA) + (RB)
RT <- [0] * 56 || MEM(EA, 1)
RA <- EA
None
# Load Halfword and Zero
+# Load Halfword and Zero
D-Form
* lhz RT,D(RA)
+Pseudo-code:
+
b <- (RA|0)
EA <- b + EXTS(D)
RT <- [0] * 48 || MEM(EA, 2)
None
# Load Halfword and Zero Indexed
+# Load Halfword and Zero Indexed
X-Form
* lhzx RT,RA,RB
+Pseudo-code:
+
b <- (RA|0)
EA <- b + (RB)
RT <- [0] * 48 || MEM(EA, 2)
None
# Load Halfword and Zero with Update
+# Load Halfword and Zero with Update
D-Form
* lhzu RT,D(RA)
+Pseudo-code:
+
EA <- (RA) + EXTS(D)
RT <- [0] * 48 || MEM(EA, 2)
RA <- EA
None
# Load Halfword and Zero with Update Indexed
+# Load Halfword and Zero with Update Indexed
X-Form
* lhzux RT,RA,RB
+Pseudo-code:
+
EA <- (RA) + (RB)
RT <- [0] * 48 || MEM(EA, 2)
RA <- EA
None
# Load Halfword Algebraic
+# Load Halfword Algebraic
D-Form
* lha RT,D(RA)
+Pseudo-code:
+
b <- (RA|0)
EA <- b + EXTS(D)
RT <- EXTS(MEM(EA, 2))
None
# Load Halfword Algebraic Indexed
+# Load Halfword Algebraic Indexed
X-Form
* lhax RT,RA,RB
+Pseudo-code:
+
b <- (RA|0)
EA <- b + (RB)
RT <- EXTS(MEM(EA, 2))
None
# Load Halfword Algebraic with Update
+# Load Halfword Algebraic with Update
D-Form
* lhau RT,D(RA)
+Pseudo-code:
+
EA <- (RA) + EXTS(D)
RT <- EXTS(MEM(EA, 2))
RA <- EA
None
# Load Halfword Algebraic with Update Indexed
+# Load Halfword Algebraic with Update Indexed
X-Form
* lhaux RT,RA,RB
+Pseudo-code:
+
EA <- (RA) + (RB)
RT <- EXTS(MEM(EA, 2))
RA <- EA
None
# Load Word and Zero
+# Load Word and Zero
D-Form
* lwz RT,D(RA)
+Pseudo-code:
+
b <- (RA|0)
EA <- b + EXTS(D)
RT <- [0] * 32 || MEM(EA, 4)
None
# Load Word and Zero Indexed
+# Load Word and Zero Indexed
X-Form
* lwzx RT,RA,RB
+Pseudo-code:
+
b <- (RA|0)
EA <- b + (RB)
RT <- [0] * 32 || MEM(EA, 4)
None
# Load Word and Zero with Update
+# Load Word and Zero with Update
D-Form
* lwzu RT,D(RA)
+Pseudo-code:
+
EA <- (RA) + EXTS(D)
RT <- [0]*32 || MEM(EA, 4)
RA <- EA
None
# Load Word and Zero with Update Indexed
+# Load Word and Zero with Update Indexed
X-Form
* lwzux RT,RA,RB
+Pseudo-code:
+
EA <- (RA) + (RB)
RT <- [0] * 32 || MEM(EA, 4)
RA <- EA
None
# Load Word Algebraic
+# Load Word Algebraic
D-Form
* lwa RT,DS(RA)
+Pseudo-code:
+
b <- (RA|0)
EA <- b + EXTS(DS || 0b00)
RT <- EXTS(MEM(EA, 4))
None
# Load Word Algebraic Indexed
+# Load Word Algebraic Indexed
X-Form
* lwax RT,RA,RB
+Pseudo-code:
+
b <- (RA|0)
EA <- b + (RB)
RT <- EXTS(MEM(EA, 4))
None
# Load Word Algebraic with Update Indexed
+# Load Word Algebraic with Update Indexed
X-Form
* lwaux RT,RA,RB
+Pseudo-code:
+
EA <- (RA) + (RB)
RT <- EXTS(MEM(EA, 4))
RA <- EA
None
# Load Doubleword
+# Load Doubleword
DS-Form
* ld RT,DS(RA)
+Pseudo-code:
+
b <- (RA|0)
EA <- b + EXTS(DS || 0b00)
RT <- MEM(EA, 8)
None
# Load Doubleword Indexed
+# Load Doubleword Indexed
X-Form
* ldx RT,RA,RB
+Pseudo-code:
+
b <- (RA|0)
EA <- b + (RB)
RT <- MEM(EA, 8)
None
# Load Doubleword with Update Indexed
+# Load Doubleword with Update Indexed
DS-Form
* ldu RT,DS(RA)
+Pseudo-code:
+
EA <- (RA) + EXTS(DS || 0b00)
RT <- MEM(EA, 8)
RA <- EA
None
# Load Doubleword with Update Indexed
+# Load Doubleword with Update Indexed
X-Form
* ldux RT,RA,RB
+Pseudo-code:
+
EA <- (RA) + (RB)
RT <- MEM(EA, 8)
RA <- EA
None
# Load Quadword
+# Load Quadword
DQ-Form
* lq RTp,DQ(RA)
+Pseudo-code:
+
b <- (RA|0)
EA <- b + EXTS(DQ || 0b0000)
RTp <- MEM(EA, 16)
None
# Load Halfword Byte-Reverse Indexed
+# Load Halfword Byte-Reverse Indexed
X-Form
* lhbrx RT,RA,RB
+Pseudo-code:
+
b <- (RA|0)
EA <- b + (RB)
load_data <- MEM(EA, 2)
None
# Load Word Byte-Reverse Indexed
+# Load Word Byte-Reverse Indexed
X-Form
* lwbrx RT,RA,RB
+Pseudo-code:
+
b <- (RA|0)
EA <- b + (RB)
load_data <- MEM(EA, 4)
None
# Load Doubleword Byte-Reverse Indexed
+# Load Doubleword Byte-Reverse Indexed
X-Form
* ldbrx RT,RA,RB
+Pseudo-code:
+
b <- (RA|0)
EA <- b + (RB)
load_data <- MEM(EA, 8)
None
# Load Multiple Word
+# Load Multiple Word
DQ-Form
* lmw RT,D(RA)
+Pseudo-code:
+
b <- (RA|0)
EA <- b + EXTS(D)
r <- RT
* andi. RA,RS,UI
+Pseudo-code:
+
RA <- (RS) & ([0]*48 || UI)
Special Registers Altered:
CR0
# OR Immediate
+# OR Immediate
D-Form
* ori RA,RS,UI
+Pseudo-code:
+
RA <- (RS) | ([0]*48 || UI)
Special Registers Altered:
None
# AND Immediate Shifted
+# AND Immediate Shifted
D-Form
* andis. RA,RS,UI
+Pseudo-code:
+
RA <- (RS) & ([0]*32 || UI || [0]*16)
Special Registers Altered:
CR0
# OR Immediate Shifted
+# OR Immediate Shifted
D-Form
* oris RA,RS,UI
+Pseudo-code:
+
RA <- (RS) | ([0]*32 || UI || [0]*16)
Special Registers Altered:
None
# XOR Immediate Shifted
+# XOR Immediate Shifted
D-Form
* xoris RA,RS,UI
+Pseudo-code:
+
RA <- (RS) ^ ([0]*32 || UI || [0]*16)
Special Registers Altered:
None
# XOR Immediate
+# XOR Immediate
D-Form
* xori RA,RS,UI
+Pseudo-code:
+
RA <- (RS) ^ ([0]*48 || UI)
Special Registers Altered:
None
# AND
+# AND
X-Form
* and RA,RS,RB (Rc=0)
* and. RA,RS,RB (Rc=1)
+Pseudo-code:
+
RA <- (RS) & (RB)
Special Registers Altered:
CR0 (if Rc=1)
# OR
+# OR
X-Form
* or RA,RS,RB (Rc=0)
* or. RA,RS,RB (Rc=1)
+Pseudo-code:
+
RA <- (RS) | (RB)
Special Registers Altered:
CR0 (if Rc=1)
# XOR
+# XOR
X-Form
* xor RA,RS,RB (Rc=0)
* xor. RA,RS,RB (Rc=1)
+Pseudo-code:
+
RA <- (RS) ^ (RB)
Special Registers Altered:
CR0 (if Rc=1)
# NAND
+# NAND
X-Form
* nand RA,RS,RB (Rc=0)
* nand. RA,RS,RB (Rc=1)
+Pseudo-code:
+
RA <- ¬((RS) & (RB))
Special Registers Altered:
CR0 (if Rc=1)
# NOR
+# NOR
X-Form
* nor RA,RS,RB (Rc=0)
* nor. RA,RS,RB (Rc=1)
+Pseudo-code:
+
RA <- ¬((RS) | (RB))
Special Registers Altered:
CR0 (if Rc=1)
# Equivalent
+# Equivalent
X-Form
* eqv RA,RS,RB (Rc=0)
* eqv. RA,RS,RB (Rc=1)
+Pseudo-code:
+
RA <- ¬((RS) ^ (RB))
Special Registers Altered:
CR0 (if Rc=1)
# AND with Complement
+# AND with Complement
X-Form
* andc RA,RS,RB (Rc=0)
* andc. RA,RS,RB (Rc=1)
+Pseudo-code:
+
RA <- (RS) & ¬(RB)
Special Registers Altered:
CR0 (if Rc=1)
# OR with Complement
+# OR with Complement
X-Form
* orc RA,RS,RB (Rc=0)
* orc. RA,RS,RB (Rc=1)
+Pseudo-code:
+
RA <- (RS) | ¬(RB)
Special Registers Altered:
CR0 (if Rc=1)
# Extend Sign Byte
+# Extend Sign Byte
X-Form
* extsb RA,RS (Rc=0)
* extsb. RA,RS (Rc=1)
+Pseudo-code:
+
s <- (RS)[56]
RA[56:63] <- (RS)[56:63]
RA[0:55] <- [s]*56
CR0 (if Rc=1)
# Extend Sign Halfword
+# Extend Sign Halfword
X-Form
* extsh RA,RS (Rc=0)
* extsh. RA,RS (Rc=1)
+Pseudo-code:
+
s <- (RS)[48]
RA[48:63] <- (RS)[48:63]
RA[0:47] <- [s]*48
CR0 (if Rc=1)
# Count Leading Zeros Word
+# Count Leading Zeros Word
X-Form
* cntlzw RA,RS (Rc=0)
* cntlzw. RA,RS (Rc=1)
+Pseudo-code:
+
n <- 32
do while n < 64
if (RS)[n] = 1 then
CR0 (if Rc=1)
# Count Trailing Zeros Word
+# Count Trailing Zeros Word
X-Form
* cnttzw RA,RS (Rc=0)
* cnttzw. RA,RS (Rc=1)
+Pseudo-code:
+
n <- 0
do while n < 32
if (RS)[63-n] = 0b1 then
CR0 (if Rc=1)
# Compare Bytes
+# Compare Bytes
X-Form
* cmpb RA,RS,RB
+Pseudo-code:
+
do n = 0 to 7
if RS[8*n:8* n+7] = (RB)[8*n:8*n+7] then
RA[8*n:8* n+7] <- [1]*8
None
# Population Count Bytes
+# Population Count Bytes
X-Form
* popcntb RA, RS
+Pseudo-code:
+
do i = 0 to 7
n <- 0
do j = 0 to 7
None
# Population Count Words
+# Population Count Words
X-Form
* popcntw RA, RS
+Pseudo-code:
+
do i = 0 to 1
n <- 0
do j = 0 to 31
None
# Parity Doubleword
+# Parity Doubleword
X-Form
* prtyd RA,RS
+Pseudo-code:
+
s <- 0
do i = 0 to 7
s <- s ^ (RS)[i*8+7]
None
# Parity Word
+# Parity Word
X-Form
* prtyw RA,RS
+Pseudo-code:
+
s <- 0
t <- 0
do i = 0 to 3
None
# Extend Sign Word
+# Extend Sign Word
X-Form
* extsw RA,RS (Rc=0)
* extsw. RA,RS (Rc=1)
+Pseudo-code:
+
s <- (RS)[32]
RA[32:63] <- (RS)[32:63]
RA[0:31] <- [s]*32
CR0 (if Rc=1)
# Population Count Doubleword
+# Population Count Doubleword
X-Form
* popcntd RA, RS
+Pseudo-code:
+
n <- 0
do i = 0 to 63
if (RS)[i] = 1 then
None
# Count Leading Zeros Doubleword
+# Count Leading Zeros Doubleword
X-Form
* cntlzd RA,RS (Rc=0)
* cntlzd. RA,RS (Rc=1)
+Pseudo-code:
+
n <- 0
do while n < 64
if (RS)[n] = 1 then
CR0 (if Rc=1)
# Count Trailing Zeros Doubleword
+# Count Trailing Zeros Doubleword
X-Form
* cnttzd RA,RS (Rc=0)
* cnttzd. RA,RS (Rc=1)
+Pseudo-code:
+
n <- 0
do while n < 64
if (RS)[63-n] = 0b1 then
CR0 (if Rc=1)
# Bit Permute Doubleword
+# Bit Permute Doubleword
X-Form
* bpermd RA,RS,RB]
+Pseudo-code:
+
perm <- [0] * 8
for i = 0 to 7
index <- (RS)[8*i:8*i+7]
* rlwinm RA,RS,SH,MB,ME (Rc=0)
* rlwinm. RA,RS,SH,MB,ME (Rc=1)
+Pseudo-code:
+
n <- SH
r <- ROTL32((RS)[32:63], n)
m <- MASK(MB+32, ME+32)
CR0 (if Rc=1)
# Rotate Left Word then AND with Mask
+# Rotate Left Word then AND with Mask
M-Form
* rlwnm RA,RS,RB,MB,ME (Rc=0)
* rlwnm. RA,RS,RB,MB,ME (Rc=1)
+Pseudo-code:
+
n <- (RB)[59:63]
r <- ROTL32((RS)[32:63], n)
m <- MASK(MB+32, ME+32)
CR0 (if Rc=1)
# Rotate Left Word Immediate then Mask Insert
+# Rotate Left Word Immediate then Mask Insert
M-Form
* rlwimi RA,RS,SH,MB,ME (Rc=0)
* rlwimi. RA,RS,SH,MB,ME (Rc=1)
+Pseudo-code:
+
n <- SH
r <- ROTL32((RS)[32:63], n)
m <- MASK(MB+32, ME+32)
CR0 (if Rc=1)
# Rotate Left Doubleword Immediate then Clear Left
+# Rotate Left Doubleword Immediate then Clear Left
MD-Form
* rldicl RA,RS,SH,MB (Rc=0)
* rldicl. RA,RS,SH,MB (Rc=1)
+Pseudo-code:
+
n <- sh[5] || sh[0:4]
r <- ROTL64((RS), n)
b <- mb[5] || mb[0:4]
CR0 (if Rc=1)
# Rotate Left Doubleword Immediate then Clear Right
+# Rotate Left Doubleword Immediate then Clear Right
MD-Form
* rldicr RA,RS,SH,ME (Rc=0)
* rldicr. RA,RS,SH,ME (Rc=1)
+Pseudo-code:
+
n <- sh[5] || sh[0:4]
r <- ROTL64((RS), n)
e <- me[5] || me[0:4]
CR0 (if Rc=1)
# Rotate Left Doubleword Immediate then Clear
+# Rotate Left Doubleword Immediate then Clear
MD-Form
* rldic RA,RS,SH,MB (Rc=0)
* rldic. RA,RS,SH,MB (Rc=1)
+Pseudo-code:
+
n <- sh[5] || sh[0:4]
r <- ROTL64((RS), n)
b <- mb[5] || mb[0:4]
CR0 (if Rc=1)
# Rotate Left Doubleword then Clear Left
+# Rotate Left Doubleword then Clear Left
MDS-Form
* rldcl RA,RS,RB,MB (Rc=0)
* rldcl. RA,RS,RB,MB (Rc=1)
+Pseudo-code:
+
n <- (RB)[58:63]
r <- ROTL64((RS), n)
b <- mb[5] || mb[0:4]
CR0 (if Rc=1)
# Rotate Left Doubleword then Clear Right
+# Rotate Left Doubleword then Clear Right
MDS-Form
* rldcr RA,RS,RB,ME (Rc=0)
* rldcr. RA,RS,RB,ME (Rc=1)
+Pseudo-code:
+
n <- (RB)[58:63]
r <- ROTL64((RS), n)
e <- me[5] || me[0:4]
CR0 (if Rc=1)
# Rotate Left Doubleword Immediate then Mask Insert
+# Rotate Left Doubleword Immediate then Mask Insert
MD-Form
* rldimi RA,RS,SH,MB (Rc=0)
* rldimi. RA,RS,SH,MB (Rc=1)
+Pseudo-code:
+
n <- sh[5] || sh[0:4]
r <- ROTL64((RS), n)
b <- mb[5] || mb[0:4]
CR0 (if Rc=1)
+# Shift Left Word
# Shift Left Word
X-Form
* slw RA,RS,RB (Rc=0)
* slw. RA,RS,RB (Rc=1)
+Pseudo-code:
+
n <- (RB)[59:63]
r <- ROTL32((RS)[32:63], n)
if (RB)[58] = 0 then
CR0 (if Rc=1)
# Shift Right Word
+# Shift Right Word
X-Form
* srw RA,RS,RB (Rc=0)
* srw. RA,RS,RB (Rc=1)
+Pseudo-code:
+
n <- (RB)[59:63]
r <- ROTL32((RS)[32:63], 64-n)
if (RB)[58] = 0 then
CR0 (if Rc=1)
# Shift Right Algebraic Word Immediate
+# Shift Right Algebraic Word Immediate
X-Form
* srawi RA,RS,SH (Rc=0)
* srawi. RA,RS,SH (Rc=1)
+Pseudo-code:
+
n <- SH
r <- ROTL32((RS)[32:63], 64-n)
m <- MASK(n+32, 63)
CR0 (if Rc=1)
# Shift Right Algebraic Word
+# Shift Right Algebraic Word
X-Form
* sraw RA,RS,RB (Rc=0)
* sraw. RA,RS,RB (Rc=1)
+Pseudo-code:
+
n <- (RB)[59:63]
r <- ROTL32((RS)[32:63], 64-n)
if (RB)[58] = 0 then
CR0 (if Rc=1)
# Shift Left Doubleword
+# Shift Left Doubleword
X-Form
* sld RA,RS,RB (Rc=0)
* sld. RA,RS,RB (Rc=1)
+Pseudo-code:
+
n <- (RB)[58:63]
r <- ROTL64((RS), n)
if (RB)[57] = 0 then
CR0 (if Rc=1)
# Shift Right Doubleword
+# Shift Right Doubleword
X-Form
* srd RA,RS,RB (Rc=0)
* srd. RA,RS,RB (Rc=1)
+Pseudo-code:
+
n <- (RB)[58:63]
r <- ROTL64((RS), 64-n)
if (RB)[57] = 0 then
CR0 (if Rc=1)
# Shift Right Algebraic Doubleword Immediate
+# Shift Right Algebraic Doubleword Immediate
XS-Form
* sradi RA,RS,SH (Rc=0)
* sradi. RA,RS,SH (Rc=1)
+Pseudo-code:
+
n <- sh[5] || sh[0:4]
r <- ROTL64((RS), 64-n)
m <- MASK(n, 63)
CR0 (if Rc=1)
# Shift Right Algebraic Doubleword
+# Shift Right Algebraic Doubleword
X-Form
* srad RA,RS,RB (Rc=0)
* srad. RA,RS,RB (Rc=1)
+Pseudo-code:
+
n <- (RB)[58:63]
r <- ROTL64((RS), 64-n)
if (RB)[57] = 0 then
CR0 (if Rc=1)
# Extend-Sign Word and Shift Left Immediate
+# Extend-Sign Word and Shift Left Immediate
XS-Form
* extswsli RA,RS,SH (Rc=0)
* extswsli. RA,RS,SH (Rc=1)
+Pseudo-code:
+
n <- sh[5] || sh[0:4]
r <- ROTL64(EXTS64(RS[32:63]), n)
m <- MASK(0, 63-n)
* stb RS,D(RA)
+Pseudo-code:
+
b <- (RA|0)
EA <- b + EXTS(D)
MEM(EA, 1) <- (RS)[56:63]
None
# Store Byte Indexed
+# Store Byte Indexed
X-Form
* stbx RS,RA,RB
+Pseudo-code:
+
b <- (RA|0)
EA <- b + (RB)
MEM(EA, 1) <- (RS)[56:63]
None
# Store Byte with Update
+# Store Byte with Update
D-Form
* stbu RS,D(RA)
+Pseudo-code:
+
EA <- (RA) + EXTS(D)
MEM(EA, 1) <- (RS)[56:63]
RA <- EA
None
# Store Byte with Update Indexed
+# Store Byte with Update Indexed
X-Form
* stbux RS,RA,RB
+Pseudo-code:
+
EA <- (RA) + (RB)
MEM(EA, 1) <- (RS)[56:63]
RA <- EA
None
# Store Halfword
+# Store Halfword
D-Form
* sth RS,D(RA)
+Pseudo-code:
+
b <- (RA|0)
EA <- b + EXTS(D)
MEM(EA, 2) <- (RS)[48:63]
None
# Store Halfword Indexed
+# Store Halfword Indexed
X-Form
* sthx RS,RA,RB
+Pseudo-code:
+
b <- (RA|0)
EA <- b + (RB)
MEM(EA, 2) <- (RS)[48:63]
None
# Store Halfword with Update
+# Store Halfword with Update
D-Form
* sthu RS,D(RA)
+Pseudo-code:
+
EA <- (RA) + EXTS(D)
MEM(EA, 2) <- (RS)[48:63]
RA <- EA
None
# Store Halfword with Update Indexed
+# Store Halfword with Update Indexed
X-Form
* sthux RS,RA,RB
+Pseudo-code:
+
EA <- (RA) + (RB)
MEM(EA, 2) <- (RS)[48:63]
RA <- EA
None
# Store Word
+# Store Word
D-Form
* stw RS,D(RA)
+Pseudo-code:
+
b <- (RA|0)
EA <- b + EXTS(D)
MEM(EA, 4) <- (RS)[32:63]
None
# Store Word Indexed
+# Store Word Indexed
X-Form
* stwx RS,RA,RB
+Pseudo-code:
+
b <- (RA|0)
EA <- b + (RB)
MEM(EA, 4) <- (RS)[32:63]
None
# Store Word with Update
+# Store Word with Update
D-Form
* stwu RS,D(RA)
+Pseudo-code:
+
EA <- (RA) + EXTS(D)
MEM(EA, 4) <- (RS)[32:63]
RA <- EA
None
# Store Word with Update Indexed
+# Store Word with Update Indexed
X-Form
* stwux RS,RA,RB
+Pseudo-code:
+
EA <- (RA) + (RB)
MEM(EA, 4) <- (RS)[32:63]
RA <- EA
None
# Store Doubleword
+# Store Doubleword
DS-Form
* std RS,DS(RA)
+Pseudo-code:
+
b <- (RA|0)
EA <- b + EXTS(DS || 0b00)
MEM(EA, 8) <- (RS)
None
# Store Doubleword Indexed
+# Store Doubleword Indexed
X-Form
* stdx RS,RA,RB
+Pseudo-code:
+
b <- (RA|0)
EA <- b + (RB)
MEM(EA, 8) <- (RS)
None
# Store Doubleword with Update
+# Store Doubleword with Update
DS-Form
* stdu RS,DS(RA)
+Pseudo-code:
+
EA <- (RA) + EXTS(DS || 0b00)
MEM(EA, 8) <- (RS)
RA <- EA
None
# Store Doubleword with Update Indexed
+# Store Doubleword with Update Indexed
X-Form
* stdux RS,RA,RB
+Pseudo-code:
+
EA <- (RA) + (RB)
MEM(EA, 8) <- (RS)
RA <- EA
None
# Store Quadword
+# Store Quadword
DS-Form
* stq RSp,DS(RA)
+Pseudo-code:
+
b <- (RA|0)
EA <- b + EXTS(DS || 0b00)
MEM(EA, 16) <- RSp
None
# Store Halfword Byte-Reverse Indexed
+# Store Halfword Byte-Reverse Indexed
X-Form
* sthbrx RS,RA,RB
+Pseudo-code:
+
b <- (RA|0)
EA <- b + (RB)
MEM(EA, 2) <- (RS) [56:63] || (RS)[48:55]
None
# Store Word Byte-Reverse Indexed
+# Store Word Byte-Reverse Indexed
X-Form
* stwbrx RS,RA,RB
+Pseudo-code:
+
b <- (RA|0)
EA <- b + (RB)
MEM(EA, 4) <- ((RS)[56:63] || (RS)[48:55] || (RS)[40:47]
None
# Store Doubleword Byte-Reverse Indexed
+# Store Doubleword Byte-Reverse Indexed
X-Form
* stdbrx RS,RA,RB
+Pseudo-code:
+
b <- (RA|0)
EA <- b + (RB)
MEM(EA, 8) <- ((RS) [56:63] || (RS)[48:55]
None
# Store Multiple Word
+# Store Multiple Word
D-Form
* stmw RS,D(RA)
+Pseudo-code:
+
b <- (RA|0)
EA <- b + EXTS(D)
r <- RS
* twi TO,RA,SI
+Pseudo-code:
+
a <- EXTS((RA)[32:63])
if (a < EXTS(SI)) & TO[0] then TRAP
if (a > EXTS(SI)) & TO[1] then TRAP
None
-# Trap Word
+# Trap Word
+# Trap Word
X-Form
* tw TO,RA,RB
+Pseudo-code:
+
a <- EXTS((RA)[32:63])
b <- EXTS((RB)[32:63])
if (a < b) & TO[0] then TRAP
None
-# Trap Doubleword Immediate
+# Trap Doubleword Immediate
+# Trap Doubleword Immediate
D-Form
* tdi TO,RA,SI
+Pseudo-code:
+
a <- (RA)
b <- EXTS(SI)
if (a < b) & TO[0] then TRAP
None
-# Trap Doubleword
+# Trap Doubleword
+# Trap Doubleword
X-Form
* td TO,RA,RB
+Pseudo-code:
+
a <- (RA)
b <- (RB)
if (a < b) & TO[0] then TRAP
None
# Integer Select
+# Integer Select
A-Form
* isel RT,RA,RB,BC
+Pseudo-code:
+
if RA=0 then a <-0
else a <- (RA)
if CR[BC+32]=1 then RT <- a
* mtspr SPR,RS
+Pseudo-code:
+
n <- spr[5:9] || spr[0:4]
switch (n)
case(13): see(Book_III_p974)
See spec 3.3.17
# Move From Special Purpose Register
+# Move From Special Purpose Register
XFX-Form
* mfspr RT,SPR
+Pseudo-code:
+
n <- spr[5:9] || spr[0:4]
switch (n)
case(129): see(Book_III_p975)
None
# Move to CR from XER Extended
+# Move to CR from XER Extended
X-Form
* mcrxrx BF
+Pseudo-code:
+
CR[4*BF+32:4*BF+35] <- XER[OV] || XER[OV32] || XER[CA] || XER[CA32]
Special Registers Altered:
CR field BF
# Move To One Condition Register Field
+# Move To One Condition Register Field
XFX-Form
* mtocrf FXM,RS
+Pseudo-code:
+
count <- 0
do i = 0 to 7
if FXM[i] = 1 then
CR field selected by FXM
# Move To Condition Register Fields
+# Move To Condition Register Fields
XFX-Form
* mtcrf FXM,RS
+Pseudo-code:
+
mask <- ([FXM[0]]*4 || [FXM[1]]*4 || [FXM[2]]*4 || [FXM[3]]*4 ||
[FXM[4]]*4 || [FXM[5]]*4 || [FXM[6]]*4 || [FXM[7]]*4)
CR <- ((RS)[32:63] & mask) | (CR & ¬mask)
CR fields selected by mask
# Move From One Condition Register Field
+# Move From One Condition Register Field
XFX-Form
* mfocrf RT,FXM
+Pseudo-code:
+
RT <- undefined
count <- 0
do i = 0 to 7
None
# Move From Condition Register
+# Move From Condition Register
XFX-Form
* mfcr RT
+Pseudo-code:
+
RT <- [0]*32 || CR
Special Registers Altered:
None
# Set Boolean
+# Set Boolean
X-Form
* setb RT,BFA
+Pseudo-code:
+
if CR[4*BFA+32] = 1 then
RT <- 0xFFFF_FFFF_FFFF_FFFF
else if CR[4*BFA+33]=1 then
None
# Move To Machine State Register
+# Move To Machine State Register
X-Form
* mtmsr RS,L
+Pseudo-code:
+
if L = 0 then
MSR[48] <- (RS)[48] | (RS)[49]
MSR[58] <- ((RS)[58] | (RS)[49]) & ¬(MSR[41] & MSR[3] & (¬(RS)[49]))
MSR
# Move From Machine State Register
+# Move From Machine State Register
X-Form
* mfmsr RT
+Pseudo-code:
+
RT <- MSR
Special Registers Altered:
* lswi RT,RA,NB
+Pseudo-code:
+
EA <- (RA|0)
if NB = 0 then n <- 32
else n <- NB
None
# Load String Word Indexed
+# Load String Word Indexed
X-Form
* lswx RT,RA,RB
+Pseudo-code:
+
b <- (RA|0)
EA <- b + (RB)
n <- XER[57:63]
None
# Store String Word Immediate
+# Store String Word Immediate
X-Form
* stswi RS,RA,NB
+Pseudo-code:
+
EA <- (RA|0)
if NB = 0 then n <- 32
else n <- NB
None
# Store String Word Indexed
+# Store String Word Indexed
X-Form
* stswx RS,RA,RB
+Pseudo-code:
+
b <- (RA|0)
EA <- b + (RB)
n <- XER[57:63]
-# System Call
+# System Call
SC-Form
* sc LEV
+Pseudo-code:
+
SRR0 <-iea CIA + 4
SRR1[33:36] <- 0
SRR1[42:47] <- 0
- SRR1[0:32] <- MSR[0:32]
+ SRR1[0:32] <- MSR[0:32]
SRR1[37:41] <- MSR[37:41]
SRR1[48:63] <- MSR[48:63]
- MSR <- new_value
+ MSR <- new_value
NIA <- 0x0000_0000_0000_0C00
Special Registers Altered:
SRR0 SRR1 MSR
# System Call Vectored
+# System Call Vectored
SC-Form
* scv LEV
+Pseudo-code:
+
LR <- CIA + 4
SRR1[33:36] <- undefined
SRR1[42:47] <- undefined
- SRR1[0:32] <- MSR[0:32]
+ SRR1[0:32] <- MSR[0:32]
SRR1[37:41] <- MSR[37:41]
SRR1[48:63] <- MSR[48:63]
- MSR <- new_value
+ MSR <- new_value
NIA <- vectored
Special Registers Altered:
LR CTR MSR
# Return From System Call Vectored
+# Return From System Call Vectored
XL-Form
* rfscv LEV
+Pseudo-code:
+
if (MSR[29:31] != 0b010) | (CTR[29:31] != 0b000) then
MSR[29:31] <- CTR[29:31]
MSR[48] <- CTR[49]
MSR
# Return From Interrupt Doubleword
+# Return From Interrupt Doubleword
XL-Form
* rfid LEV
+Pseudo-code:
+
MSR[51] <- (MSR[3] & SRR1[51]) | ((¬MSR[3] & MSR[51]))
MSR[3] <- (MSR[3] & SRR1[3])
if (MSR[29:31] != 0b010) | (SRR1[29:31] != 0b000) then
MSR
# Hypervisor Return From Interrupt Doubleword
+# Hypervisor Return From Interrupt Doubleword
XL-Form
* hrfid LEV
+Pseudo-code:
+
if (MSR[29:31] != 0b010) | (HSRR1[29:31] != 0b000) then
MSR[29:31] <- HSRR1[29:31]
MSR[48] <- HSRR1[48] | HSRR1[49]
projects / libreriscv.git / commitdiff