Fix muxAB logic

diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg
index 24247d3cf8c654efc4184f835e95433b2b0d43af..4b566f0a6403150a4ebb8bb115d43a6018fcf3e8 100644 (file)
--- a/passes/pmgen/ice40_dsp.pmg
+++ b/passes/pmgen/ice40_dsp.pmg
@@ -187,10 +187,9 @@ code clock clock_pol sigO sigCD sigCD_signed
 
                // Loading value into output register is not
                //   supported unless using accumulator
-               if (muxAB && sigCD != sigO) {
-                       if (muxAB != addAB)
+               if (muxAB) {
+                       if (sigCD != sigO)
                                reject;
-
                        if (muxA)
                                sigCD = port(muxAB, \B);
                        else if (muxB)